CMOS Analog Integrated Circuit Design using the Inversion Coefficient

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7 Basic building blocks

7.1 Introduction

Circuits and systems are built in a hierarchical way, usually using a top-down approach, from high level description down to circuits and devices. In this book we are using a bottom-up approach, constructing systems, like filters, from basic circuits and devices. In this Chapter we are looking at the simplest circuits that can be built with one or a few transistors to form the basic building blocks that are then used in more complex circuits like amplifiers or filters.

Figure 1: Single-transistor gain stages.

We start with circuits made of a single transistor (plus eventually some bias sources). Considering that usually the bulk is not an active terminal, a single transistor can basically be connected in three different ways as illustrated in Figure 1. We can identify three elementary gain stages depending which of the source, gate or drain terminal of the transistor is connect to a DC or AC ground: common-source, common-drain and common-gate.

The common-source (CS) circuit is basically a transconductance amplifier delivering a small-signal output current \(\Delta I_{out}\) proportional to the small-signal input voltage \(\Delta V_{in}\). The ratio of the output current to input voltage is the transconductance \(G_m\). The common-source stage has very high input and output impedances.

The common-drain (CD) is biased from the bottom by a constant bias current \(I_b\). The \(V_{GS}\) voltage remains constant and therefore a change of the gate input voltage \(\Delta V_{in}\) is copied to the output resulting in a change \(\Delta V_{out}\) of the source output voltage about equal to the change of the input voltage. It therefore has a voltage gain close to unity. For this reason the common-drain is also called a voltage follower or source follower. It has a high capacitive input impedance and a low output resistance \(R_{out} = 1/G_{ms}\).

The common-gate (CG) stage is biased with a constant bias voltage \(V_b\) at its gate. The small-signal input current \(\Delta I_{in}\) is transferred to the drain as a drain current \(\Delta I_{out} = \Delta I_{in}\) with a unity current gain. It has a low input impedance \(R_{in} = 1/G_{ms}\) and high output impedance.

We now will analyze each of the elementary gain stages in more details below starting with the common-source gain stage.

7.2 Elementary gain cells (common-source stages)

7.2.1 Gain cell with resistive load

7.2.1.1 Large-signal analysis

The simplest common-source (CS) gain stage is the \(G_m\)-\(R\) circuit shown in Figure 2 (a). Note that the bias current is set by a DC input voltage which is not shown in the schematic. We will start looking at the large signal voltage transfer characteristic and then perform a small-signal analysis.

(a) Schematic.

(b) Large-signal transfer characteristic.

Figure 2: CS gain cell with resistive load or \(G_m\)-\(R\) gain cell.

When sweeping the DC input voltage \(V_{in}\), the output voltage \(V_{out}\) changes as shown in Figure 3 (a). For a zero input voltage, the current is zero and the output voltage is equal to the supply voltage \(V_{DD}\). As soon as the input voltage increases and becomes close to the threshold voltage, the current starts to increase and the output voltage decreases as \(V_{out}=V_{DD} - R_L \cdot I_D(V_{in})\). The slope of the large-signal DC transfer characteristic is the small-signal DC voltage gain. At some point the current becomes large enough for \(V_{out}\) to become equal to the transistor saturation voltage \(V_{DSsat}\). Increasing the input voltage further pushes the transistor out of saturation and the small-signal voltage gain drops.

We now will perform a small-signal analysis.

7.2.1.2 Small-signal analysis

(a) Small-signal circuit.

(b) Small-signal transfer function.

Figure 3: Small-signal analysis

The small-signal schematic of the \(G_m\)-\(R\) gain cell of Figure 2 (a) is shown in Figure 3 (a), which also includes the noise source \(I_{nM}\) for the noise due to transistor M and \(I_{nRL}\) due to the thermal noise coming from the load resistance \(R_L\). To derive the small-signal transfer function, we set the noise sources to zero, resulting in \[\begin{equation}\label{eqn:Av_gain_cell} A_v(s) \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = \frac{A_{dc}}{1+s/\omega_c} \end{equation}\] where \[\begin{align} A_{dc} &= -G_m\,R_L,\\ \omega_c &= \frac{1}{R_L\,C_L}, \end{align}\] with \(A_{dc} = -G_m \cdot R_L\) the DC voltage gain and \(\omega_c\) the cut-off frequency. The gain-bandwidth product (\(GBW\)) or unity gain frequency (\(\omega_u\)) is then given by \[\begin{equation} GBW = \omega_u = |A_{dc}| \cdot \omega_c = \frac{G_m}{C_L}. \end{equation}\] The cut-off frequency is set by the load resistance \(R_L\) and capacitance \(C_L\), whereas the gain-bandwidth product is set by the transconductance \(G_m\) and the load capacitance \(C_L\).

The magnitude of the small-signal DC gain can be written as \[\begin{equation} |A_{dc}| = G_m\,R_L = \frac{G_m}{I_b}\,R_L\,I_b = \frac{G_m}{I_b} \, (V_{DD}-V_{out}) \end{equation}\] with \[\begin{equation} \frac{G_m}{I_b} = \begin{cases} \frac{1}{n\,U_T} & \textsf{WI and sat.}\\ \frac{2}{n\,V_{DSsat}} & \textsf{SI and sat. (with VS)}. \end{cases} \end{equation}\]
The small-signal voltage gain \(|A_{dc}|\) is therefore maximum for the highest \(G_m/I_b\) ratio (which occurs in weak inversion) and highest \(R_L\,I_b\) product, hence the lowest output voltage that still keeps the transistor in saturation \(V_{out,min} = V_{DSsat}\). The maximum small-signal DC voltage gain is therefore bounded by \[\begin{equation} |A_{dc}| < \frac{V_{DD}}{n\,U_T}. \end{equation}\] This means that voltage scaling is unavoidably reducing the small-signal DC voltage of this \(G_m\)-\(R\) amplifier. For example if \(V_{DD} = 1.6\,V\) and \(n\,U_T = 40\,mV\), we have \(|A_{dc}| < 40\). Note that is actually true for most of the amplifiers.

7.2.1.3 Noise analysis

We now will derive the PSD of the output noise. To do this we first set the small-signal input voltage to zero \(\Delta V_{in}=0\) and calculate the output voltage due to \(I_{nM}\) and \(I_{nRL}\). Since the two noise sources come in parallel, we need to compute only one transfer function (which is actually a transimpedance) between the noise sources and the output voltage. The PSD of the output voltage fluctuations is then given by \[\begin{equation}\label{eqn:Snout1} S_{V_{nout}} = |Z_{mn}(\omega)|^2 \cdot S_{I_{nout}} \end{equation}\] where \(Z_{mn}\) is the transimpedance \[\begin{equation}\label{eqn:GmRL_Zmn} Z_{mn}(s) = \frac{R_L}{1+s/\omega_c} \end{equation}\] and \[\begin{equation} S_{I_{nout}} = S_{I_{nM}} + S_{I_{nRL}} = 4 k_B\,T\,\left(G_n + \frac{1}{R_L}\right). \end{equation}\] \(G_n\) is the noise conductance at the drain of M including both the thermal and flicker noise \[\begin{equation} G_n = \gamma_n\,G_m + G_m^2\,\frac{\rho_n}{W\,L\,f}. \end{equation}\]

The output noise voltage PSD can be referred to the input by dividing \(S_{V_{nout}}\) by the square magnitude of the transfer function \[\begin{equation} S_{V_{nin}} = \frac{S_{V_{nout}}}{|A_v(f)|^2} = \frac{|Z_{mn}(f)|^2}{|A_v(f)|^2}\,S_{I_{nout}} = \frac{S_{I_{nout}}}{G_m^2}. \end{equation}\] The input-referred noise PSD can also be written as \[\begin{equation} S_{V_{nin}} = 4 k_B\,T\,R_{nin}, \end{equation}\] where the input-referred noise resistance \(R_{nin}\) is given by \[\begin{equation} R_{nin} = R_{nt} + R_{nf}(f). \end{equation}\] \(R_{nt}\) is the input-referred thermal noise resistance \[\begin{equation} R_{nt} =\frac{\gamma_n}{G_m} + \frac{1}{G_m^2\,R_L}. \end{equation}\] and \(R_{nf}\) is the input-referred flicker noise resistance which only depends on the flicker noise coming from the transistor M \[\begin{equation} R_{nf} = \frac{\rho_n}{W\,L\,f}. \end{equation}\]

We can write the input-referred thermal noise resistance as \[\begin{equation} R_{nt} = \frac{\gamma_n}{G_m}\,(1+\eta_{th}) \end{equation}\] where \(\eta_{th}\) represents the thermal noise contribution of the load resistance to the input-referred noise, compared to that of the transistor \[\begin{equation} \eta_{th} = \frac{1}{\gamma_n\,G_m\,R_L} = \frac{1}{\gamma_n\,|A_{dc}|}. \end{equation}\] Since the noise of the load resistance occurs at the output, its relative contribution to the input-referred thermal noise resistance can be minimized by maximizing the DC voltage gain \(|A_{dc}|\).

We can also write the input-referred thermal noise resistance as \[\begin{equation} R_{nt} = \frac{\gamma_{neq}}{G_m} \end{equation}\] where \(\gamma_{neq}\) is the equivalent thermal noise excess factor accounting for both noise sources and given by \[\begin{equation} \gamma_{neq} = \gamma_n\,(1+\eta_{th}) = \gamma_n + \frac{1}{G_m\,R_L} = \gamma_n + \frac{1}{|A_{dc}|} \cong \gamma_n \quad \textsf{for $|A_{dc}| \gg 1$}. \end{equation}\] For a small-signal DC gain \(|A_{dc}| \gg 1\), the input-referred thermal noise resistance is dominated by the contribution of the transistor. As the gain degrades because of voltage scaling, the noise contribution of the load resistance to the input-referred thermal noise resistance also increases. This highlights the challenge of designing high gain and low-noise amplifiers at low-voltage.

We can also calculate the total output thermal noise voltage. Since the noise transfer function given by \(\eqref{eqn:GmRL_Zmn}\) is a 1^st-order low-pass filter, its equivalent noise bandwidth is simply given by \[\begin{equation} B_n = \frac{\pi}{2}\,f_c = \frac{\pi}{2}\,\frac{1}{2\,\pi\,R_L\,C_L} = \frac{1}{4\,R_L\,C_L}. \end{equation}\] The thermal noise voltage variance at the output can then be obtained as \[\begin{equation} \begin{split} V_{nout}^2 &= Z_{mn}(0)^2\,4\,k_B\,T\left(\gamma_n\,G_m + \frac{1}{R_L}\right)\,B_n = \frac{k_B\,T}{C_L}\,(\gamma_n\,G_m\,R_L + 1)\\ & \cong \frac{\gamma_n\,k_B\,T}{C_L}\,G_m\,R_L = \frac{\gamma_n\,k_B\,T}{C_L}\,A_{dc}. \end{split} \end{equation}\] Without surprise we get \(k_B\,T/C\) noise. Now in this special case the bandwidth is set by \(R_L\) and \(C_L\) whereas the thermal noise depends on both the transistor and resistance thermal noise. If the transistor is considered as noiseless (i.e. \(\gamma_n=0\)), the thermal noise output voltage variance is simply \(V_{nout}^2 = k_B\,T/C_L\), which is consistent with the fact that \(R_L\) sets at the same time the noise level and the noise bandwidth (like in the case of the passive 1^st-order low-pass filter). Adding the transistor thermal noise adds the \(\gamma_n\,G_m\,R_L\) term, which usually dominates for high DC gain.

7.2.2 Gain cell with diode-connected transistor load

7.2.2.1 Large-signal analysis

(a) Schematic.

(b) Transistor currents.

(c) Transfer characteristic.

Figure 4: Gain cell with diode-connected transistor load.

We can replace the resistor of the \(G_m\)-\(R\) gain cell of Figure 2 (a) by a pMOS transistor connected as diode (gate connected to the drain) as shown in Figure 4 (a). Of course the load has now the nonlinear characteristic of a MOS transistor. Figure 4 (b) shows the currents of M₁ and M₂ and the cross point corresponds to the operating point. Figure 4 (c) shows the large-signal input-output characteristic obtained by sweeping the input voltage and looking at the output voltage. Similarly to Figure 2 (b), increasing \(V_{in}\) makes the output decrease. As we sweep the input voltage, we basically can identify 4 different regions of operations:

• region 4 where the current is very small and hence both transistors M₁ and M₂ are in weak inversion and the output voltage is close to \(V_{DD}\),
• region 3 where M₁ is in weak inversion and M₂ in strong inversion,
• region 2 where both M₁ and M₂ are in strong inversion and finally
• region 1 where the output voltage becomes smaller than the saturation voltage of M₁ pushing it out of saturation into the linear region.

The magnitude of the small-signal DC voltage gain corresponding to these operating regions is given by \[\begin{equation} |A_{dc}| = \frac{G_{m1}}{G_{m2}} = \begin{cases} \sqrt{\frac{\beta_1\,n_2}{\beta_2\,n_1}} = \frac{n_2}{n_1}\,\frac{V_{DSsat2}}{V_{DSsat1}} & \textsf{M1, M2 in SI (Region 2)},\\ \frac{1}{n_1\,U_T}\,\sqrt{\frac{n_2\,I}{2\,\beta_2}} = \frac{n_2}{n_1}\,\frac{V_{DSsat2}}{2\,U_T} & \textsf{M1 in WI and M2 in SI (Region 3)},\\ \frac{n_2}{n_1} \cong 1 & \textsf{M1 and M2 in WI (Region 4)}. \end{cases} \end{equation}\]

The small-signal DC voltage gain \(|A_{dc}|\) is maximum in region 3 corresponding to M₁ biased in weak inversion and M₂ biased in strong inversion. Similarly to the \(G_m\)-\(R\) gain cell, the small-signal voltage gain is bounded by the supply voltage \[\begin{equation} |A_{dc}| < \frac{V_{DD}}{2\,U_T}. \end{equation}\] The maximum achievable gain for \(V_{DD}=1.6\,V\) is \(|A_{dc}|=30.8\).

7.2.2.2 Small-signal analysis

(a) Small-signal circuit.

(b) Small-signal transfer function.

Figure 5: Small-signal analysis.

The small-signal schematic of Figure 4 (a) is shown in Figure 5 (a) where the load resistance is now replaced by the transconductance \(G_{m2}\). We have neglected the output conductances of M₁ and M₂ because they come in parallel with \(G_{m2}\) and usually we can consider that \(G_{ds1}, G_{ds2} \ll G_{m2}\). The transfer function remains identical to \(\eqref{eqn:Av_gain_cell}\) with \[\begin{align} A_{dc} &= -\frac{G_{m1}}{G_{m2}},\\ \omega_c &= \frac{G_{m2}}{C_L},\\ \omega_u &= |A_{dc}| \cdot \omega_c = \frac{G_{m1}}{C_L}. \end{align}\]

We have seen that the DC gain is maximum for M₁ biased in WI and M₂ in SI. The transconductances are then given by \[\begin{align} G_{m1} &= \frac{I_b}{n_1\,U_T},\\ G_{m2} &= \frac{2\,I_b}{n_2\,V_{P2}} = \frac{2\,I_b}{n_2\,V_{DSsat2}} = \frac{2\,I_b}{V_{BG2}-V_{T0p}}. \end{align}\] The magnitude of the DC gain can then be written as \[\begin{equation} |A_{dc}| = \frac{G_{m1}}{G_{m2}} = \frac{n_2\,V_{DSsat2}}{2 n_1\,U_T} = \frac{V_{BG2}-V_{T0p}}{2 n_1\,U_T}. \end{equation}\] Since M₁ is biased in weak inversion its saturation voltage is about \(V_{DSsat1}=4\,U_T\). The maximum voltage gain is then directly related to the supply voltage according to \[\begin{equation} A_{dc,max} \cong -\frac{V_{DD}-V_{T0p}-4\,U_T-V_{pp}}{2 n_1 \, U_T}, \end{equation}\] where \(V_{pp}\) is the peak-to-peak output signal voltage swing. The voltage gain is ultimately limited by the supply voltage (and the pMOS threshold voltage).

7.2.2.3 Noise analysis

The output noise PSD is given by \(\eqref{eqn:Snout1}\) with \[\begin{equation} Z_{mn}(s) = -\frac{1}{G_{m2}}\,\frac{1}{1+s/\omega_c} \end{equation}\] and \[\begin{equation} S_{I_{nout}} = S_{I_{n1}} + S_{I_{n2}} = 4 k_B\,T\,\left(G_{n1} + G_{n2}\right). \end{equation}\] \(G_{ni}\) is the noise conductance at the drain of M₁ and M₂ including both the thermal and flicker noise \[\begin{equation}\label{eqn:7:gni} G_{ni} = \gamma_{ni}\,G_{mi} + G_{mi}^2\,\frac{\rho_i}{W_i\,L_i\,f} \quad \textsf{for $i=1,2$}, \end{equation}\] with \(\rho_1=\rho_n\) and \(\rho_2=\rho_p\).

The input-referred noise resistance for \(\omega \ll \omega_c\) is given by \[\begin{equation} R_{nin} = R_{nt} + R_{nf}(f). \end{equation}\] \(R_{nt}\) is the input-referred thermal noise resistance given by \[\begin{equation} R_{nt} =\frac{\gamma_{n1}}{G_{m1}}\,\left(1+\eta_{th}\right) = \frac{\gamma_{neq}}{G_{m1}}, \end{equation}\] where \(\gamma_{neq}\) is the amplifier thermal noise excess factor given by \[\begin{equation} \gamma_{neq} = \gamma_{n1} \cdot \left(1+\eta_{th}\right). \end{equation}\] Parameter \(\eta_{th}\) represents the contribution of M₂ to the input-referred thermal noise resistance relative to that of M₁ and is given by \[\begin{equation} \eta_{th} = \frac{\gamma_{n2}}{\gamma_{n1}}\,\frac{G_{m2}}{G_{m1}} = \frac{\gamma_{n2}}{\gamma_{n1}}\,\frac{1}{|A_{dc}|} = \frac{\gamma_{n2}}{\gamma_{n1}}\,\frac{2 n_1\,U_T}{n_2\,V_{DSsat2}} = \frac{\gamma_{n2}}{\gamma_{n1}}\,\frac{2 n_1\,U_T}{V_{BG2}-V_{T0p}}. \end{equation}\] Since the latter cannot be avoided, we want to minimize the contribution of M₂ and hence minimize \(\eta_{th}\). This can be done by making the DC gain \(|A_{dc}| = G_{m1}/G_{m2}\) as large as possible.

\(R_{nf}\) is the input-referred flicker noise resistance which can be written as \[\begin{equation} R_{nf} = \frac{\rho_n}{W_1\,L_1\,f}\,(1+\eta_{fl}), \end{equation}\] where \(\eta_{fl}\) is defined as \[\begin{equation} \eta_{fl} = \frac{\rho_p}{\rho_n}\,\left(\frac{G_{m2}}{G_{m1}}\right)^2\,\frac{W_1\,L_1}{W_2\,L_2} = \frac{\rho_p}{\rho_n}\,\frac{1}{A_{dc}^2}\,\frac{W_1\,L_1}{W_2\,L_2}. \end{equation}\] Similarly to \(\eta_{th}\), parameter \(\eta_{fl}\) represents the contribution of M₂ to the input-referred flicker noise resistance relative to the contribution of M₁. To minimize the contribution of M₂ to the input-referred flicker noise, we need to minimize \(\eta_{fl}\). Since \(\eta_{fl}\) is inversely proportional to the square of the DC gain, assuming that M₁ and M₂ have about the same gate area and that \(\rho_n\) and \(\rho_p\) are about equal, the contribution of M₂ is usually negligible. If it would turn out not to be the case, we can use the additional degree of freedom related to the gate area ratio by increasing \(W_2\,L_2\) keeping \(W_1\,L_1\) constant.

The corner frequency \(f_k\) is defined as the frequency at which \(R_{nf}(f=f_k)=R_{nt}\). It is given by \[\begin{equation} f_k = \frac{\rho_n}{W_1\,L_1} \cdot \frac{G_{m1}}{\gamma_{n1}} \cdot \frac{1+\eta_{fl}}{1+\eta_{th}}. \end{equation}\]

Quarto Notebook: Basic G_m Gain Stage

Thie Quarto Notebook presents a design example of the gain cell with diode-connected transistor load.

7.2.3 Gain cell with current source load

7.2.3.1 Large-signal analysis

The DC gain of the CS with a diode-connected pMOS of Figure 4 (a) is limited to how big we can make the \((V_{BG2}-V_{T0p})/(2 n_1\,U_T)\) ratio. To further increase the DC gain we can replace the diode-connected pMOS transistor by a current source as shown in Figure 6 (a).

(a) Schematic.

(b) Transistor currents.

(c) Transfer characteristic.

Figure 6: Gain cell with current source load.

Figure 6 (b) shows the current \(I_1\) of M₁ and the current \(I_2\) of M₂ as a function of the output voltage \(V_{out}\). The operating point corresponds to the intersection of the nMOS and pMOS output characteristic as shown in Figure 6 (b) by circles. The case 1 corresponds to M₁ in the linear region and M₂ in the saturation region. Case 3 corresponds to the opposite situation where M₁ is in saturation and M₂ in the linear region. The large-signal transfer characteristic \(V_{out}\) versus \(V_{in}\) is sketched in Figure 6 (c). We immediately see that the small-signal voltage gain, corresponding to the derivative of the large-signal transfer characteristic, is maximum in the region corresponding to both M₁ and M₂ biased in saturation. This maximum small-signal DC voltage gain is given by \[\begin{equation} |A_{dc}| = \frac{G_{m1}}{G_{ds1}+G_{ds2}} = \begin{cases} V_M \, \sqrt{\frac{2\,\beta_1}{n_1\,I}} = \frac{2\,V_M}{n_1\,V_{DSsat1}} & \textsf{M1 in SI},\\ \frac{V_M}{n_1\,U_T} & \textsf{M1 in WI}, \end{cases} \end{equation}\] where \(V_M\) is the modulation voltage that combines the channel length modulation voltages of M₁ and M₂ \[\begin{equation} \frac{1}{V_M} \triangleq \frac{1}{V_{M1}} + \frac{1}{V_{M2}} \cong \frac{1}{\lambda_n\,L_{eff1}} + \frac{1}{\lambda_p\,L_{eff2}}. \end{equation}\] The small-signal DC gain is therefore maximum for M₁ biased in weak inversion.

7.2.3.2 Small-signal analysis

(a) Small-signal schematic.

(b) Voltage gain transfer function.

Figure 7: Small-signal analysis of the CS stage gain cell with current source load.

The small-signal schematic of Figure 6 (a) is shown in Figure 7 (a), where the noisy current source \(I_{n1}\) represents the noise coming from M₁ and \(I_{n23}\) represents the noise coming from M₂ and M₃. The small-signal transfer function is identical to \(\eqref{eqn:Av_gain_cell}\) with \[\begin{align} A_{dc} &= -\frac{G_{m1}}{G_{out}},\\ \omega_c &= \frac{G_{out}}{C_L},\\ \omega_u &= |A_{dc}| \cdot \omega_c = \frac{G_{m1}}{C_L}, \end{align}\] where \(G_{out} = G_{ds1}+G_{ds2}\).

7.2.3.3 Noise analysis

It is easy to show that the input-referred noise resistance is given by \[\begin{equation} R_{nin} = R_{nt} + R_{nf} = R_{n1} + \left(\frac{G_{m2}}{G_{m1}}\right)^2\,(R_{n2}+R_{n3}) = R_{n1} + \left(\frac{G_{m2}}{G_{m1}}\right)^2\,2\,R_{n2}, \end{equation}\] where we have assumed that M₂ is identical to M₃. \(R_{ni}\) are the gate-referred noise resistances of M₁, M₂ and M₃ given by \[\begin{equation}\label{eqn:Rni} R_{ni} = \frac{\gamma_{ni}}{G_{mi}} + \frac{\rho_i}{W_i\,L_i\,f} \quad \textsf{for $i=1,2,3$}. \end{equation}\]

The input-referred thermal noise resistance is given by \[\begin{equation} R_{nt} =\frac{\gamma_{n1}}{G_{m1}}\,\left(1+\eta_{th}\right) = \frac{\gamma_{neq}}{G_{m1}}. \end{equation}\] Parameter \(\eta_{th}\) represents the contributions of M₂ and M₃ to the input-referred thermal noise resistance relative to that of M₁. It is defined as \[\begin{equation} \eta_{th} = 2\,\frac{\gamma_{n2}}{\gamma_{n1}}\,\frac{G_{m2}}{G_{m1}}. \end{equation}\] Since the contribution of M₁ cannot be avoided because it appears directly at the input, we want to minimize the contribution of M₂ and hence minimize \(\eta_{th}\). Since M₁ and M₂ share the same current, \(\eta_{th}\) can be minimized by biasing M₁ in WI and M₂ in SI. The transconductances are then given by \[\begin{align} G_{m1} &= \frac{I}{n_1\,U_T},\\ G_{m2} &= \frac{2\,I}{n_2\,V_{P2}} = \frac{2\,I}{V_{BG2}-V_{T0p}}. \end{align}\] The \(G_{m2}/G_{m1}\) gain is then given by \[\begin{equation} \frac{G_{m2}}{G_{m1}} = \frac{2\,n_1\,U_T}{V_{BG2}-V_{T0p}}. \end{equation}\] The minimum value of \(G_{m2}/G_{m1}\) is therefore set by the maximum \(V_{BG2}\) that can keep M₁ and M₂ in saturation.

We can also define \(\gamma_{neq}\) as the amplifier thermal noise excess factor which is given by \[\begin{equation}\label{eqn:gammaneq_cs} \gamma_{neq} = \gamma_{n1} \cdot \left(1+\eta_{th}\right). \end{equation}\] If we can make \(\eta_{th} \ll 1\), then the amplifier thermal noise excess factor is minimum and equal to that of transistor M₁ \(\gamma_{neq} \cong \gamma_{n1}\).

Note

Note that biasing the current mirror M₂ and M₃ in strong inversion is also good for optimizing the current matching.

The input-referred flicker noise resistance \(R_{nf}\) is given by \[\begin{equation} R_{nf} = \frac{\rho_n}{W_1\,L_1\,f}\,(1+\eta_{fl}), \end{equation}\] where \(\eta_{fl}\) is defined as \[\begin{equation} \eta_{fl} = 2\,\frac{\rho_p}{\rho_n}\,\left(\frac{G_{m2}}{G_{m1}}\right)^2\,\frac{W_1\,L_1}{W_2\,L_2}, \end{equation}\] and represents the contribution of M₂ and M₃ to the input-referred flicker noise resistance relative to the contribution of M₁. To minimize the contribution of M₂ and M₃ to the input-referred flicker noise, we need to minimize \(\eta_{fl}\). In some technologies, there is a big difference between the flicker noise of nMOS and pMOS devices resulting in a \(\rho_p/\rho_n\) that can be much larger than 1. Minimizing \(G_{m2}/G_{m1}\) might then not be enough to minimize \(\eta_{fl}\). We can then use the additional degrees of freedom on the gate area, increasing \(W_2\,L_2\) at the cost of increasing the parasitic capacitance at the gate node of the current mirror. This has no impact on the signal transfer function of the CS gain stage because the current in M₂ and M₃ is only a bias current. As we will see later, the situation is different in the case of the simple OTA for example where the pMOS current mirror also carries the current signal. Increasing the current mirror gate area increases the parasitic capacitance and reduces the non-dominant pole which is not desirable.

The corner frequency \(f_k\) is then given by \[\begin{equation} f_k = \frac{\rho_n}{W_1\,L_1}\,\frac{G_{m1}}{\gamma_{n1}}\,\frac{1+\eta_{fl}}{1+\eta_{th}}. \end{equation}\]

The CS gain stage will be studied in more details in Section 7.3, where we will optimize the design for minimum power consumption.

7.2.4 The CMOS inverter as a gain cell

We can modify the CS gain cell of Figure 6 (a) and use the pMOS transistor M₂ as an active device by connecting its gate to the input voltage. We then get the CMOS inverter shown in Figure 8 (a).

(a) Schematic.

(b) Transistor currents.

(c) Transfer characteristic.

Figure 8: The CMOS inverter as a gain cell.

The CMOS inverter shown in Figure 8 (a) can actually be used as a very current-efficient gain cell, because the bias current is used twice, in the pMOS and nMOS transistors (this is called current sharing). The currents \(I_1\) and \(I_2\) of M₁ and M₂ are plotted in Figure 8 (b) versus the output voltage \(V_{out}\). The operating point correspond to the intersection of the blue and red curves are indicated by circles. The large-signal input-output characteristic is plotted in Figure 8 (c). The small-signal DC voltage gain becomes maximum when both transistors M₁ and M₂ are biased in saturation. It is given by \[\begin{equation} |A_{dc}| = \frac{G_{m1}+G_{m2}}{G_{ds1}+G_{ds2}} = \begin{cases} \frac{V_M}{n\,U_T} & \textsf{M1 and M2 in WI},\\ \frac{V_M}{\sqrt{I_b}}\,\left(\sqrt{\frac{2\,\beta_1}{n_1}} + \sqrt{\frac{2\,\beta_2}{n_2}}\right) & \textsf{M1 and M2 in SI}, \end{cases} \end{equation}\] where \[\begin{align} \frac{1}{V_M} &= \frac{1}{V_{M1}} + \frac{1}{V_{M2}},\\ \frac{1}{n} &= \frac{1}{n_1} + \frac{1}{n_2}. \end{align}\]

7.2.4.1 Large-signal analysis in weak inversion

A key large-signal feature of the CMOS inverter is that the output current is not limited by a constant biasing current source as it is the case for the CS gain stage of Figure 6 (a). It can operate in class AB delivering an output current larger than the quiescent bias current. The CS gain stage of Figure 6 (a) operates in class A. Although it can also deliver a negative output current \(I_{out}\) larger than the bias current, on the other hand the output current \(I_{out}\) is limited on the positive side by the bias current.

Figure 9: Schematic used for the large-signal analysis.

To highlight this feature, we now will perform a large-signal analysis using the schematic shown in Figure 9 and assuming that both transistors M₁ and M₂ are biased in weak inversion and saturation. For the purpose of this analysis we have added a voltage source that is connected to the output node and which sets the output voltage to \(V_{DD}/2\). The drain currents are given by \[\begin{align} I_n &= I_{D0n} \cdot e^{\frac{V_{in}}{n_n\,U_T}},\label{eqn:In}\\ I_p &= I_{D0p} \cdot e^{\frac{V_{DD}-V_{in}}{n_p\,U_T}},\label{eqn:Ip} \end{align}\] where \[\begin{align} I_{D0n} &= I_{specn} \cdot e^{-\frac{V_{T0n}}{n_n\,U_T}},\\ I_{D0p} &= I_{specp} \cdot e^{-\frac{V_{T0p}}{n_p\,U_T}}, \end{align}\] with \[\begin{align} I_{specn} &= I_{specn\Box} \cdot \frac{W_n}{L_n},\\ I_{specp} &= I_{specp\Box} \cdot \frac{W_p}{L_p}. \end{align}\]

Defining \(V_b\) as the quiescent input voltage such that the output current is zero, and hence \(I_p=I_n=I_b\), we can write \[\begin{equation} I_b = I_{D0n} \cdot e^{\frac{V_b}{n_n\,U_T}} = I_{D0p} \cdot e^{\frac{V_{DD}-V_b}{n_p\,U_T}}. \end{equation}\] We can then express \(I_{D0n}\) and \(I_{D0p}\) as \[\begin{align} I_{D0n} &= I_b \cdot e^{\frac{-V_b}{n_n\,U_T}},\label{eqn:ID0n}\\ I_{D0p} &= I_b \cdot e^{\frac{V_b-V_{DD}}{n_p\,U_T}}.\label{eqn:ID0p} \end{align}\] Replacing \(\eqref{eqn:ID0n}\) and \(\eqref{eqn:ID0p}\) in \(\eqref{eqn:In}\) and \(\eqref{eqn:Ip}\) results in \[\begin{align} I_n &= I_b \cdot e^{\frac{V_{in}-V_b}{n_n\,U_T}},\label{eqn:In2}\\ I_p &= I_b \cdot e^{-\frac{V_{in}-V_b}{n_p\,U_T}},\label{eqn:Ip2} \end{align}\]

The output current can then be written as \[\begin{equation} I_{out} = I_p - I_n = I_b \cdot \left[e^{-\frac{V_{in}-V_b}{n_n\,U_T}} - e^{\frac{V_{in}-V_b}{n_n\,U_T}}\right]. \end{equation}\]

Assuming that \(n_n = n_p = n\), the normalized output current can finally be written as \[\begin{equation} i_{out} \triangleq \frac{I_{out}}{I_b} = - 2\,\sinh(v_{in}-v_b) \end{equation}\] where \(v_{in} \triangleq V_{in}/(n U_T)\) and \(v_b \triangleq V_b/(n U_T)\).

Figure 10: Normalized output current versus input voltage.

The output current \(I_{out}\) normalized to the quiescent current \(I_b\) is plotted in Figure 10 together with the currents \(I_n\) and \(I_p\) of the nMOS and pMOS transistors also normalized to \(I_b\). We see that the current is ideally not limited hence the inverter can operate as a class AB transconductance amplifier. Contrary to the differential pair where the output current is limited by the bias current \(2 I_b\), the output current of the inverter can be much larger than the bias current \(I_b\) flowing in M₁ and M₂ for \(V_{in}=V_b\). The current will actually be limited by the supply voltage and the supply series resistance.

Quarto Notebook: The CMOS Inverter as an Amplifier

This Quarto notebook illustrates the CMOS inverter discussed above by a design example and simulations.

(a) Reset phase \(\Phi_1\) [1].

(b) Amplification phase \(\Phi_2\) [1].

Figure 11: Switched-capacitor implementation of the CMOS inverter used to set the bias current \(I_b\) [1].

One of the difficulty arising with the CMOS inverter is how to properly set the bias current, because the current flowing in the pMOS and nMOS transistors is very dependent on the supply voltage. A simple way to solve this problem is to use a switched-capacitor (SC) implementation as shown in Figure 11. This amplifier operates with two non-overlapping phases: phase \(\Phi_1\), shown in Figure 11 (a), during which the amplifier is reset and the bias current is applied, and an amplification phase \(\Phi_2\), shown in Figure 11 (b), during which the input signal is amplified. The amplifier operates in the following way. During the reset phase \(\Phi_1\), the input is disconnected and the left side of capacitor \(C_1\) is connected to ground by means of switch S₁. The drains of M₁ and M₂ are also disconnected from the output by opening switch S₃. The drain and gate of transistor M₁ are connected together by closing switch S₂. The gates of M₂ and M₃ are connected together by closing switch S₄ so that they operate as a current mirror. The bias current \(I_b\) is then applied to M₃ and copied to M₂ and M₁. Transistors M₁ and M₂ are now correctly biased with the desired bias current \(I_b\). At the end of the reset phase \(\Phi_1\), switch S₂ and S₄ are opened. The bias voltages are then freezed on \(C_1\) and \(C_2\), so that the same bias current flows after opening switch S₂ and S₄. Finally switch S₁ is connected back to the input and the output is connected back by closing switch S₃ as shown in Figure 11 (b). The amplifier can now amplify the input signal with transistors M₁ and M₂ correctly biased with a bias current equal to \(I_b\).

The SC CMOS inverter of Figure 11 has an additional property of 1/f noise cancellation that is discussed in more details in Chapter ???.

Note

Note that the bias current might be a bit different because of the nonidealities of the switches. Indeed, when opening a switch it injects some charges that change the voltages at its source and drain. These nonidealities are discussed in more details in Chapter ???.

Now that we are able to set and control the bias current and operating point, we can proceed with the small-signal analysis.

7.2.4.2 Small-signal analysis

(a) Small-signal schematic.

(b) Voltage gain transfer function.

Figure 12: Small-signal analysis of the CMOS inverter gain stage.

From the CMOS inverter small-signal schematic of Figure 12 (a), we see that it is actually identical to that of the CS gain stage with \[\begin{align} G_m &= G_{m1} + G_{m2},\\ G_{out} &= G_{ds1} + G_{ds2},\\ I_n &= I_{n1} + I_{n2}. \end{align}\] The CMOS inverter transconductance is therefore the sum of the nMOS and pMOS transconductance. If we assume that both M₁ and M₂ are biased in WI and that \(n=n_1=n_2\), then nMOS and pMOS transconductances are equal \(G_{m1} = G_{m2} = I_b/(n\,U_T)\). It means that the CMOS inverter has twice the transconductance compared to the CS stage for the same bias current \(I_b\) and is therefore two times more current efficient.

The small-signal transfer function is identical to \(\eqref{eqn:Av_gain_cell}\) with \[\begin{align} A_{dc} &= -\frac{G_m}{G_{out}} = -\frac{G_{m1}+G_{m2}}{G_{ds1}+G_{ds2}},\\ \omega_c &= \frac{G_{out}}{C_L} = \frac{G_{ds1}+G_{ds2}}{C_L},\\ \omega_u &= |A_{dc}| \cdot \omega_c = \frac{G_m}{C_L} = \frac{G_{m1}+G_{m2}}{C_L}. \end{align}\] The CMOS inverter can achieve a GBW product that is twice that obtained for the CS gain stage for the same bias current.

7.2.4.3 Noise analysis

It is easy to show that the input-referred noise resistance is given by \[\begin{equation} R_{nin} = R_{nt} + R_{nf} = \frac{G_{m1}^2\,R_{n1}+G_{m2}\,R_{n2}}{G_m^2} = \frac{G_{m1}^2\,R_{n1}+G_{m2}\,R_{n2}}{(G_{m1}+G_{m2})^2}, \end{equation}\] where \(R_{ni}\) are the transistor gate-referred noise resistance given by \(\eqref{eqn:Rni}\) with \(\rho_1=\rho_n\) and \(\rho_2=\rho_p\). If we assume that both M₁ and M₂ are biased in WI and that \(n=n_1=n_2\) and \(\gamma_{n1}=\gamma_{n2}\), then nMOS and pMOS transconductances are equal \(G_{m1} = G_{m2} = I_b/(n\,U_T)\) and the input-referred noise resistance reduces to half the noise resistance of M₁ or M₂ \[\begin{equation} R_{nin} \cong \frac{R_{n1}}{2} = \frac{R_{n2}}{2}. \end{equation}\] The input-referred noise resistance of the CMOS inverter, including both thermal and flicker noise, is about half that of the CS gain stage for the same bias current.

The input-referred thermal noise resistance is given by \[\begin{equation} R_{nt} = \frac{\gamma_{n1}\,G_{m1}+\gamma_{n2}\,G_{m2}}{(G_{m1}+G_{m2})^2}. \end{equation}\] Again, if we assume that both M₁ and M₂ are biased in WI and that \(n=n_1=n_2\) and \(\gamma_{n1}=\gamma_{n2}\), the input-referred thermal noise resistance reduces to \[\begin{equation} R_{nt} = \frac{\gamma_{n1}}{2\,G_{m1}}. \end{equation}\] The equivalent thermal noise excess factor \(\gamma_{neq}\) is given by \[\begin{equation} \gamma_{neq} = G_m \cdot R_{nt} = \frac{\gamma_{n1}\,G_{m1}+\gamma_{n2}\,G_{m2}}{(G_{m1}+G_{m2})} = \gamma_{n1}. \end{equation}\] the equivalent thermal noise excess factor \(\gamma_{neq}\) is equal to the thermal noise excess factor of a single transistor \(\gamma_{n1}\) or \(\gamma_{n2}\). It is therefore smaller than that of the CS gain stage given by \(\eqref{eqn:gammaneq_cs}\).

The flicker noise input-referred noise resistance is then given by \[\begin{equation} R_{nf} = \left(\frac{G_{m1}}{G_{m1}+G_{m2}}\right)^2\,\frac{\rho_n}{W_1\,L_1\,f} + \left(\frac{G_{m2}}{G_{m1}+G_{m2}}\right)^2\,\frac{\rho_p}{W_2\,L_2\,f} \end{equation}\]

The input-referred flicker noise resistance \(R_{nf}\) is given by \[\begin{equation} R_{nf} = \left(\frac{G_{m1}}{G_{m1}+G_{m2}}\right)^2\,\frac{\rho_n}{W_1\,L_1\,f}\,(1+\eta_{fl}), \end{equation}\] where \(\eta_{fl}\) is defined as \[\begin{equation} \eta_{fl} = \frac{\rho_p}{\rho_n}\,\left(\frac{G_{m2}}{G_{m1}}\right)^2\,\frac{W_1\,L_1}{W_2\,L_2}. \end{equation}\] For M₁ and M₂ biased in WI, we have \(G_{m1}=G_{m2}\), the input-referred flicker noise resistance reduces to \[\begin{equation} R_{nf} \cong \frac{1}{4}\,\frac{\rho_n}{W_1\,L_1\,f}\,(1+\eta_{fl}) \end{equation}\] and if additionally we can consider that \(\rho_n=\rho_p\) and \(W_1\,L_1=W_2\,L_2\), then \(\eta_{fl}=1\) and \[\begin{equation} R_{nf} \cong \frac{1}{2}\,\frac{\rho_n}{W_1\,L_1\,f}. \end{equation}\] The input-referred flicker noise resistance is then equal to half that of a single transistor M₁ or M₂.

The CMOS inverter can be used as very current-efficient amplifier or transconductor. The bias current can be imposed by using a switched-capacitor (SC) network with two non-overlapping phases [1]. It is therefore well suited to the implementation of SC circuits and filters [2]. The CMOS inverter will be studied in more details in Chapter ??? dedicated to SC circuits and filters.

We now will have a closer look at the CS gain stage and investigate how it can be designed to minimize power consumption.

7.3 Common-source Stage Optimization using the Inversion Coefficient

In this section, we will have a closer look at the CS gain stage with current source load of Figure 6 trying to optimize it for different specifications. In order to do this we will consider the current source load as an ideal current source as shown in Figure 13.

Figure 13: Schematic of the open-loop common-source (CS) gain stage.

The schematic of the common-source (CS) stage in open-loop (OL) configuration is shown in Figure 13. To design this circuit according to some specifications on the gain, bandwidth or noise, we need to find the bias current \(I_b\) and the aspect ratio \(W/L\) that satisfies the given specifications.

Before we proceed with the optimization, we will first perform a small-signal analysis in the next section.

7.3.1 Small-signal analysis

Figure 14: Small-signal schematic of the open-loop (OL) common-source (CS) gain stage including the feedback capacitance.

The small-signal schematic of the open-loop (OL) common-source (CS) stage of Figure 13 is shown in Figure 14. Compared to the small-signal schematic of Figure 7 (a), we now also have included the feedback capacitance \(C_F\) due to the gate-to-drain extrinsic capacitance. We will see below that this feedback capacitance \(C_F\) introduces a positive zero and limits the gain magnitude at high frequency.

It is straightforward to show that the transfer function is given by \[\begin{equation}\label{eqn:7:gain_with_cf} A(s) \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = A_{dc} \cdot \frac{1-s/\omega_z}{1+s/\omega_p} \end{equation}\] where \[\begin{align} A_{dc} &= -G_m \cdot R_{ds},\\ \omega_z &= \frac{G_m}{C_F},\\ \omega_p &= \frac{1}{R_{ds}\,C_{out}}, \end{align}\] with \(A_{dc} = -G_m \cdot R_{ds}\) the DC voltage gain, \(\omega_z\) the zero (in the right half plan), \(\omega_p\) the pole and \(C_{out}=C_L+C_F\) the total load capacitance at the output node including the feedback capacitance. The gain-bandwidth product (\(GBW\)) or unity gain frequency (\(\omega_u\)) is then given by \[\begin{equation} GBW = \omega_u = |A_{dc}| \cdot \omega_p = \frac{G_m}{C_{out}}. \end{equation}\] The magnitude and phase of the transfer function given by \(\eqref{eqn:7:gain_with_cf}\) is plotted in Figure 15. We can see that the positive zero introduced by the feedback capacitance makes the phase turn by an additional \(90^\circ\) and limits the gain magnitude at high frequency to \[\begin{equation} \lim_{s \to \infty} A(s) = \frac{C_F}{C_L+C_F}, \end{equation}\]

Figure 15: Bode plot of the small-signal transfer function of the CS OL amplifier.

7.3.2 Minimum current for a given transconductance

In this section we want to answer the following question:

Question

What is the minimum current \(I_b\) and transistor size (aspect ratio \(W/L\)) in order for the CS OL gain stage of Figure 13 to achieve a given transconductance?

To answer this question we first rewrite the current as \[\begin{equation} I_b = I_{spec\Box} \cdot \frac{W}{L} \cdot IC \end{equation}\] and the transconductance as \[\begin{equation} G_m = \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC), \end{equation}\] where \(g_{ms}(IC)\) is the normalized source transconductance which only depends on \(IC\) according to \[\begin{equation} g_{ms} \triangleq \frac{G_{ms}}{G_{spec}} = \frac{n\,G_m}{G_{spec}} = \frac{\sqrt{4 IC+1}-1}{2} \end{equation}\] for a long-channel transistor and \[\begin{equation} g_{ms} = \frac{\sqrt{4 IC+1+(\lambda_c\,IC)^2}-1}{2+\lambda_c^2\,IC} \end{equation}\] for a short-channel transistor accounting for velocity saturation with parameter \(\lambda_c\).

We then need to solve the following set of equation for \(I_b\) and \(W/L\) \[\begin{align} G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\]

This leads to the following normalized results \[\begin{align} i_b &\triangleq \frac{I_b}{G_m \cdot n U_T} = \frac{IC}{g_{ms}},\\ AR &\triangleq \frac{W}{L} \cdot \frac{I_{spec\Box}}{G_m \cdot n U_T} = \frac{1}{g_{ms}}. \end{align}\] The normalized bias current \(i_b\) and aspect ratio \(AR\) are plotted versus \(IC\) for various values of \(\lambda_c\) in Figure 16.

Figure 16: Normalized bias current \(i_b\) and aspect ratio \(AR\) versus inversion coefficient \(IC\) for achieving a constant transconductance \(G_m\).

From Figure 16, we see that we can reduce the current \(i_b\) when moving from strong inversion to moderate inversion reaching a minimum in weak inversion. The loss of transconductance resulting from a reduction of \(IC\) is compensated by an increase of \(W/L\) as shown by the blue curves, resulting in a very large transistor and a drastic area increase. Moderate inversion turns out to be a good trade-off between low current and acceptable area for achieving a given transconductance.

We also see the impact of velocity saturation in Figure 16 where at a given inversion coefficient \(IC\) in strong inversion, we require far more current to achieve the same transconductance for a short-channel transistor than for a long-channel transistor.

7.3.3 Minimum current for a given gain-bandwidth product (no self-loading)

We now will answer the question:

Question

What is the minimum bias current to achieve a given gain-bandwidth product for a given load capacitance neglecting the effect of self-loading?

We first rewrite the gain-bandwidth product as \[\begin{equation} \omega_u = \frac{G_m}{C_L} = \omega_L \cdot \frac{W}{L} \cdot g_{ms}, \end{equation}\] where \[\begin{equation} \omega_L \triangleq \frac{I_{spec\Box}}{n U_T \cdot C_{out}}. \end{equation}\]

To answer this question we need to solve the following set of equations for \(I_b\) and \(W/L\) \[\begin{align} \omega_u &= \omega_L \cdot \frac{W}{L} \cdot g_{ms},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\] Since the load capacitance \(C_L\) is assumed constant, the problem is similar to imposing a given transconductance. With a slightly different normalization we get the same normalized functions as before \[\begin{align} i_b &\triangleq \frac{I_b}{G_m \cdot n U_T} \cdot \frac{1}{\Omega} = \frac{IC}{g_{ms}},\\ AR &\triangleq \frac{W}{L} \cdot \frac{1}{\Omega} = \frac{1}{g_{ms}}. \end{align}\] with \[\begin{equation} \Omega \triangleq \frac{\omega_u}{\omega_L}. \end{equation}\]

A different normalization reduces to the same trade-off than constant \(G_m\) and hence the normalized bias current \(i_b\) and aspect \(AR\) are identical to the one plotted in Figure 16 for various values of \(\lambda_c\). Moderate inversion again turns out to be a good trade-off between low current and acceptable area for achieving a given gain-bandwidth product.

When moving to moderate and weak inversion, the transistor can become very large. The parasitic capacitance at the transistor drain can then no more be ignored. We will analyze the impact of self-loading in the next section.

7.3.4 Minimum current for a given gain-bandwidth product including self-loading (long-channel)

7.3.4.1 Analysis

Figure 17: Schematic of the open-loop common-source (CS) gain stage including the self-loading capacitances at the drain.

When optimizing the OL CS amplifier for low current consumption, the transistor is often biased in moderate or even weak inversion leading to a large transistor and therefore an increased output capacitance due to the self-loading from the parasitic capacitances connected to the drain. We now want to answer the following question:

Question

What is the minimum bias current \(I_b\) and transistor size (aspect ratio \(W/L\)) in order for the OL CS gain stage to achieve a given gain-bandwidth product accounting for the effect of self-loading?

As shown in Figure 17, the self-loading capacitances include the junction capacitance at the drain \(C_{BDj}\) and the feedback capacitance \(C_F\). The junction capacitance \(C_{BDj}\) is given by \[\begin{equation} \begin{split} C_{BDj} &= 2 H_{dif} \cdot W \cdot C_J + 2(2 H_{dif}+W) \cdot C_{JSW}\\ &= 4 H_{dif} \cdot C_{JSW} + 2(H_{dif} \cdot C_J + C_{JSW}) \cdot W \end{split} \end{equation}\] where \(C_J\) is the bottom junction capacitance per unit area, \(C_{JSW}\) is the side-wall capacitance per unit length and \(H_{dif}\) is the half minimum diffusion width, which is imposed by the layout rules. Of course the junction capacitances per area and per length \(C_J\) and \(C_{JSW}\) are bias dependent since they depend on the drain-to-bulk voltage, but we consider their highest value obtained for a zero drain-to-bulk voltage (worst case).

Since the transistor is biased in saturation, the intrinsic gate-to-drain capacitance \(C_{GDi}\) is negligible. The feedback capacitance is therefore due to the extrinsic capacitance which is given by \[\begin{equation} C_F = C_{GDe} \cdot W, \end{equation}\] where \(C_{GDe}\) is the extrinsic capacitance per unit width which includes the overlap and fringing field capacitance and is given by \[\begin{equation} C_{GDe} = C_{GDo} + C_{GDf}. \end{equation}\] where \(C_{GDo}\) is the overlap capacitance per unit width and \(C_{GDf}\) is the fringing field capacitance per unit width.

Note

Note that the fringing field capacitance per unit width is ignored in this 180 nm technology but may become of the same order of magnitude than the overlap capacitance per unit width in more advanced technologies.

The total transistor parasitic capacitance at the drain can then be written as \[\begin{equation} C_D = C_{D0} + C_{DW} \cdot W, \end{equation}\] where \(C_{D0}\) is the part of \(C_D\) that doesn’t scale with \(W\) and \(C_{DW} \cdot W\) is the part of \(C_D\) that scales with \(W\) \[\begin{align} C_{D0} &= 4 H_{dif} \cdot C_{JSW},\\ C_{DW} &= 2(H_{dif} \cdot C_J + C_{JSW}) + C_{GDe}. \end{align}\] We can add \(C_{D0}\) to \(C_{L0}\) and define the total load capacitance \(C_L\) that doesn’t scale with \(W\) as \[\begin{equation} C_L = C_{L0} + C_{D0}. \end{equation}\]

In order to achieve a certain bandwidth we need to have a certain transconductance for a given load capacitance. In order to maximize the current efficiency, we should bias the transistor in weak inversion. This leads to a large transistor and therefore large parasitic capacitances which will impact the bandwidth. Imposing the bandwidth, at some point the capacitance becomes so large that it is no more possible to achieve the required transconductance in weak inversion for the desired bandwidth.

Question

Does this mean that there is a minimum current for the OL CS amplifier to achieve a certain gain-bandwidth product?

To answer this question we need to solve the following set of equations for \(I_b\) and \(W\) assuming a given length \(L\) \[\begin{align} \omega_u &= \frac{G_m}{C_{out}},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ C_{out} &= C_L + C_{DW} \cdot W,\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\]

Solving for \(I_b\) and \(W/L\) leads to the following normalized solutions \[\begin{align} i_b &\triangleq \frac{I_b}{I_{pec\Box} \cdot \Omega} = \frac{IC}{g_{ms}(IC) - \Theta},\\ AR &\triangleq \frac{W/L}{\Omega} =\frac{1}{g_{ms} - \Theta}, \end{align}\] where \[\begin{align} \Omega &\triangleq \frac{\omega_u}{\omega_L},\\ \omega_L &\triangleq \frac{I_{spec\Box}}{n U_T \cdot C_L},\\ \Theta &\triangleq \frac{\omega_u}{\omega_W},\\ \omega_W &\triangleq \frac{I_{spec\Box}}{n U_T \cdot C_{DW} \cdot L} = \frac{I_{spec}}{n U_T \cdot C_{DW} \cdot W}. \end{align}\]

Note

There is no straightfoward interpretation of the normalization frequencies \(\omega_L\) and \(\omega_W\). We can however describe the normalization frequency \(\omega_L\) as the unity gain frequency of a square transistor (i.e. with equal width and length \(W=L\)) biased at an inversion coefficient \(IC =\) 2 for which the normalized source transconductance \(g_{ms}\) is equal to 1 and which is loaded only by a capacitance \(C_L = C_{L0} + C_{D0}\), ignoring the part that is scaling with \(W\).

The normalization frequency \(\omega_W\) can be understood as the unity gain frequency of a very wide transistor for which the load capacitance is then dominated by the self-loading capacitance \(W\,C_{DW}\) and biased at an inversion coefficient \(IC =\) 2 for which the normalized source transconductance \(g_{ms}\) is equal to 1 \[\begin{equation} \frac{G_m}{W\,C_{DW}} = \frac{I_{spec}\,g_{ms}(IC=2)}{n U_T\,C_{DW}\,W} = \frac{I_{spec\Box}\,W/L}{n U_T\,C_{DW}\,W} = \frac{I_{spec\Box}}{n U_T\,C_{DW}\,L}. \end{equation}\]

The normalized current \(i_b\) and normalized aspect ratio \(AR\) are plotted in Figure 18 for three values of parameter \(\Theta\). The normalized current \(i_b\) is plotted alone in Figure 19 versus \(IC\) for more values of \(\Theta\).

Figure 18: Normalized bias current \(i_b\) anbd aspect ratio \(AR\) versus inversion coefficient \(IC\).

Figure 19: Normalized bias current \(i_b\) versus inversion coefficient \(IC\).

From Figure 18 and Figure 19, we clearly see that there is a minimum current for a given value of parameter \(\Theta\). We can find the optimum inversion coefficient \(IC_{opt}\) which is given by \[\begin{equation}\label{eqn:icopt} IC_{opt} = \left(\sqrt{\Theta \cdot (1+\Theta)} + \Theta + \frac{1}{2}\right)^2 - \frac{1}{4} = 2 \Theta \cdot (1+\Theta) + (1+2\Theta) \cdot \sqrt{\Theta \cdot (1+\Theta)}. \end{equation}\] For \(\Theta \ll 1\), \(\eqref{eqn:icopt}\) reduces to \[\begin{equation} IC_{opt} \cong 2 \Theta + \sqrt{\Theta}. \end{equation}\]

From the above figure we also see that there is a minimum inversion coefficient \(IC_{lim}\) below which the desired gain-bandwidth product \(GBW\) can no more be achieved \[\begin{equation} IC_{lim} = \Theta \cdot (1+\Theta) \cong \Theta, \end{equation}\] which is about equal to \(\Theta\) for small values of \(\Theta\). \(IC_{lim}\) correspond to the dashed black vertical lines in Figure 19.

The optimum normalized current is given by \[\begin{equation}\label{eqn:ibopt} i_{bopt} \triangleq i_b(IC_{opt}) = 1 + 2\Theta +2\sqrt{\Theta \cdot (1+\Theta)}, \end{equation}\] which only depends on \(\Theta\).

Parameter \(\Theta\) can be eliminated from equations \(\eqref{eqn:ibopt}\) and \(\eqref{eqn:icopt}\) resulting in an expression of \(i_{opt}\) in terms of \(IC_{opt}\) \[\begin{equation} i_{bopt} = \sqrt{4 IC_{opt} + 1} \end{equation}\] which is plotted as a dashed red line in Figure 18 and Figure 19.

To the optimum current also corresponds an optimum transistor width \(W\) and hence and optimum normalized \(W/L\) given by \[\begin{equation}\label{eqn:aropt} AR_{opt} \triangleq AR(IC_{opt}) = \frac{1}{\sqrt{\Theta \cdot (1+\Theta)}}, \end{equation}\] which also only depends on \(\Theta\).

As above, parameter \(\Theta\) can be eliminated between equations \(\eqref{eqn:icopt}\) and \(\eqref{eqn:aropt}\) giving an expression of \(AR_{opt}\) in terms of \(IC_{opt}\) \[\begin{equation} AR_{opt} = \frac{\sqrt{4 IC_{opt} + 1}}{IC_{opt}}, \end{equation}\] which is plotted as a dashed red line in Figure 20.

Figure 20: Normalized aspect ratio \(AR\) versus inversion coefficient \(IC\).

We see from Figure 20 that the transistor width increases first as \(1/\sqrt{IC}\) in strong inversion and then as \(1/IC\) in weak inversion making the transistor quickly very large until \(IC\) reaches \(IC_{lim}\) where the width becomes infinity. The dots correspond to the \(AR\) obtained for \(IC_{opt}\).

The optimum parameters \(IC_{opt}\), \(i_{bopt}\) and \(AR_{opt}\) are plotted versus \(\Theta\) in Figure 21. We can see that the optimum inversion coefficient is always located in moderate or eventually weak inversion.

Figure 21: Optimum parameters versus \(\Theta\).

Quarto Notebook: Common-source Stage Optimization using the Inversion Coefficient

This Quarto notebook illustrates the optimization of the above CS OL gain stage for GBW including the self-loading capacitance by a design example and simulations.

7.3.5 Minimum current for given GBW and DC gain

7.3.5.1 Analysis

We can actually use the additional degree of freedom, namely the transistor length \(L\) (which has been arbitrarily set in the previous example), to set the DC gain. To this purpose we can use the simple output conductance model given by \[\begin{equation} G_{ds} \cong \frac{I_D}{\lambda \cdot L}. \end{equation}\]

We now need to solve the following set of equations \[\begin{align} \omega_u &= \frac{G_m}{C_L} = \frac{G_m}{C_{L0} + C_{DW} \cdot W},\\ A_{dc} &= \frac{G_m}{G_{ds}} = \frac{G_m \cdot \lambda \cdot L}{I_b},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\] for \(I_b\), \(W\), \(L\) and \(G_m\). This leads to the following normalized results \[\begin{align} i_b &\triangleq \frac{I_b}{I_{norm}} = \frac{g_{ms} \cdot IC}{g_{ms}^2 - \xi \cdot IC} = \frac{g_{ms}/IC}{(g_{ms}/IC)^2 - \xi/IC},\\ w &\triangleq \frac{W}{W_{norm}} = \frac{IC}{g_{ms}^2 - \xi \cdot IC},\\ \ell &\triangleq \frac{L}{L_{norm}} = \frac{IC}{g_{ms}}, \end{align}\] where \[\begin{align} \xi &\triangleq \frac{C_{DW} \cdot (n U_T)^2}{I_{spec\Box} \cdot \lambda} \cdot A_{dc} \cdot \omega_u,\\ I_{norm} & \triangleq n\,U_T \cdot C_{L0} \cdot \omega_u,\\ W_{norm} &\triangleq \frac{C_{L0} \cdot (n U_T)^2}{I_{spec\Box} \cdot \lambda} \cdot A_{dc} \cdot \omega_u,\\ L_{norm} & \triangleq \frac{n U_T}{\lambda} \cdot A_{dc}. \end{align}\]

The normalized bias current, width and length are plotted in Figure 22, Figure 23 and Figure 24 for different values of the parameter \(\xi\).

Figure 22: Normalized bias current \(i_b\) versus inversion coefficient \(IC\) for given gain-bandwidth product and DC gain.

Figure 23: Normalized width \(w\) versus inversion coefficient \(IC\) for given gain-bandwidth product and DC gain.

Figure 24: Normalized length \(\ell\) versus inversion coefficient \(IC\) for given gain-bandwidth product and DC gain.

Quarto Notebook: Common-source Stage Optimization using the Inversion Coefficient

This Quarto Notebook illustrates the optimization of the CS OL gain stage for GBW and DC gain including the self-loading capacitance by a design example and simulations.

7.4 Cascode stages (common-gate stages)

7.4.1 Simple cascode stage

(a) Simple cascode schematic.

(b) Folded cascode schematic.

Figure 25: Cascode stages.

The schematic of the simple cascode stage is shown in Figure 25 (a). It is made of a driver transistor M₁ and a common-gate stage M₂, often called the cascode transistor, sharing the same bias current \(I_b\). The purpose of the cascode transistor is to decouple the ouput node from the drain of the driver transistor M₁. This allows to siginificantly increase the output resistance and decrease the Miller effect.

Figure 25 (b) shows an alternative implementation of the cascode stage Figure 25 (a) called the folded cascode. The cascode transistor M₂ is now implemented with a pMOS transistor instead of an nMOS. When used in an differential OTA, the folded cascode can provide a higher output voltage swing compared to the telescopic OTA. However this comes at the cost of almost twice the power consumption than the telescopic OTA.

To illustrate the main features of the cascode stage we will start with a small-signal analysis.

7.4.1.1 Small-signal analysis

Figure 26: Small-signal schematic of the cascode stage of Figure 25 (a) for the calculation of the equivalent transconductance.

The small-signal schematic corresponding to Figure 25 (a) for the derivation of the equivalent transconductance is shown in Figure 26. Note that the output is short-circuited to the AC ground for calculating the short-circuit output current and the corresponding transconductance. The equivalent transconductance is then given by \[\begin{equation} G_{meq} \triangleq \left.\frac{\Delta I_{out}}{\Delta V_{in}}\right|_{\Delta V_{out}=0} = G_{m1} \cdot \frac{G_{ms2} + G_{ds2}}{G_{ms2} + G_{ds1} + G_{ds2}} \cong G_{m1}, \end{equation}\] which shows that assuming \(G_{ms2} \gg G_{ds1}, G_{ds2}\), the equivalent transconductance of the cascode stage is equal to the transconductance of the driver transistor M₁. This result is expected since the cascode transistor is a common gate stage which has a unity current gain so that the current coming from the driver transistor M₁ is directly steered to the output.

Figure 27: Small-signal schematic of the cascode stage of Figure 25 (a) for the calculation of the output conductance.

The small-signal schematic for the calculation of the output conductance is shown in Figure 27. The output conductance is given by \[\begin{equation} G_{out} \triangleq \frac{\Delta I_{out}}{\Delta V_{out}} = \frac{G_{ds1} G_{ds2}}{G_{ms2} + G_{ds1} + G_{ds2}} \cong \frac{G_{ds1}}{G_{ms2}/G_{ds2}}, \end{equation}\] which is equal to the output conductance of M₁, \(G_{ds1}\), divided by the intrinsic voltage gain of the cascode transistor \(G_{ms2}/G_{ds2}\). This means that, at low-frequency, the output conductance of a single transistor can be reduced by adding a cascode stage at the cost of some voltage headroom to maintain M₂ in saturation.

The small-signal voltage gain is then given by \[\begin{equation} A_v \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = -\frac{G_{meq}}{G_{out}} = -\frac{G_{m1}\,(G_{ms2} + G_{ds2})}{G_{ds1}\,G_{ds2}} \cong -\frac{G_{m1}}{G_{ds1}}\,\frac{G_{ms2}}{G_{ds2}}. \end{equation}\] which corresponds to the gain of the cascade of two CS gain stage. So we can achieve the same gain as the cascade of two CS gain stage but at about half the current thanks to the current sharing between the driver M₁ and the cascode transistor M₂. We only need a bit more voltage headroom to make sure that M₂ is biased in saturation. To minimize this voltage headroom and maximize the transconductance efficiency, M₂ should be biased in weak inversion.

(a) Simple cascode schematic including parasitic capacitances at the cascode node 1.

(b) Small-signal schematic of the cascode stage of Figure 28 (a) for the calculation of the output admittance including the parasitic capacitance \(C_{p1}\).

Figure 28: Cascode stage showing the parasitic capacitance at the cascode node 1.

The impact of the parasitic capacitance at node 1 on the output admittance can be investigated by adding the capacitance as shown in Figure 28 (b). The output admittance then becomes \[\begin{equation} Y_{out} = G_{out} \cdot \frac{1+s/\omega_z}{1+s/\omega_p}, \end{equation}\] where \[\begin{align} G_{out} &\cong \frac{G_{ds1} G_{ds2}}{G_{ms2}},\\ \omega_z &\triangleq \frac{G_{ds1}}{C_{p1}},\\ \omega_p &\triangleq \frac{G_{ms2}}{C_{p1}}. \end{align}\]

Figure 29: Effect of the parasitic capacitance \(C_{p1}\) on the output admittance \(Y_{out}\).

The magnitude of \(Y_{out}\) versus frequency is sketched in Figure 29. At low-frequency, i.e. for \(\omega \ll \omega_z \ll \omega_p\), the output admittance is equal to the output conductance \(Y_{out} \cong G_{out}\). However for \(\omega_z \ll \omega_p \ll \omega\), the output admittance increases to the output conductance of M₂ \(Y_{out} \cong G_{ds2}\). We see that the cascode effect is lost. This can easily be understood since for \(\omega_p \ll \omega\), the cascode node 1 is shortened to the AC ground and the voltage controlling the source of M₂ is zero leaving the output conductance of M₂ only in the small-signal schematic of Figure 28 (b).

7.4.1.2 Noise analysis

Figure 30: Small-signal schematic of the cascode stage of Figure 25 (a) for the noise calculation.

To calculate the output noise PSD we can use the schematic shown in Figure 30. The output noise current is then given by \[\begin{equation} \Delta I_{nout} = \frac{G_{ms2} + G_{ds2}}{G_{ms2} + G_{ds1} + G_{ds2}} \cdot I_{n1} + \frac{G_{ds1}}{G_{ms2} + G_{ds1} + G_{ds2}} \cdot I_{n2} \cong I_{n1} + \frac{I_{n2}}{G_{ms2}/G_{ds1}}, \end{equation}\] for \(G_{ms2} \gg G_{ds1}, G_{ds2}\). We see that the contribution to the output noise current of the cascode stage \(I_{n2}\) is actually divided by \(G_{ms2}/G_{ds1}\). Provided that this gain can be made sufficiently large and that both transistor have the same noise, the noise of the cascode stage can be made negligible compared to the noise due to M₁. Ultimately if \(G_{ds1}=0\), the noise current \(I_{n2}\) in the small-signal schematic of Figure 30 is trapped in the cascode transistor, which means that it actually circulates in the cascode transistor M₂ through \(G_{ms2}\) and hence does not reach the output.

The PSD of the output noise current fluctuations \(\Delta I_{nout}\) can be written as \[\begin{equation} S_{\Delta I_{nout}} = 4 k_B\,T\,G_{nout}(f), \end{equation}\] where the output noise conductance \(G_{nout}\) is given by \[\begin{equation} G_{nout}(f) \cong G_{n1}(f) + \left(\frac{G_{ds1}}{G_{ms2}}\right)^2 G_{n2}(f) \end{equation}\] where the noise conductances are given by \(\eqref{eqn:7:gni}\).

The input-referred noise is obtained by dividing \(G_{nout}\) by \(G_{meq}^2\), resulting in \[\begin{equation} R_{nin} = \frac{G_{nout}(f)}{G_{meq}^2} \cong \frac{G_{nout}(f)}{G_{m1}^2} \cong \frac{G_{n1}(f)}{G_{m1}^2} + \left(\frac{G_{ds1}}{G_{m1}\,G_{ms2}}\right)^2\;G_{n2}(f). \end{equation}\] It can be decomposed into the thermal and flicker noise components according to \[\begin{equation} R_{nin} = R_{nt} + R_{nf}(f) \end{equation}\] where \(R_{nt}\) is the total input-referred thermal noise given by \[\begin{equation} R_{nt} \cong \frac{\gamma_{n1}}{G_{m1}} + \left(\frac{G_{ds1}}{G_{m1}}\right)^2 \frac{\gamma_{n2}}{n_2\,G_{ms2}} = \frac{\gamma_{n1}}{G_{m1}} \cdot (1+\eta_{th}), \end{equation}\] where \(\eta_{th}\), given by \[\begin{equation} \eta_{th} \cong \frac{\gamma_{n2}}{n_2\,\gamma_{n1}} \cdot \frac{G_{ds1}^2}{G_{m1}\,G_{ms2}}, \end{equation}\] represents the contribution of the cascode transistor M₂ to the input-referred thermal noise relative to that of M₁. Since \(\gamma_{n1}\) and \(\gamma_{n2}\) are of the same order of magnitude and \(G_{m1},G_{ms2} \gg G_{ds1}\), this results in \(\eta_{th} \ll 1\), meaning that the contribution of M₂ is negligible compared to that of M₁ (at low frequency).

The noise excess factor of the cascode gain stage is given by \[\begin{equation} \gamma_{cas} \triangleq G_{meq} \cdot R_{nt} \cong G_{m1} \cdot R_{nt} = \gamma_{n1} \cdot (1+\eta_{th}) \cong \gamma_{n1}. \end{equation}\] The thermal noise excess factor of the cascode gain stage is about equal to the thermal noise excess factor of the driver transistor M₁.

The input-referred flicker noise resistance \(R_{nf}(f)\) is given by \[\begin{equation}\label{eqn:p1:Rnf} R_{nf}(f) \cong \frac{\rho_n}{f\,W_1 L_1} + \left(\frac{G_{ds1}}{G_{m1}}\right)^2 \frac{\rho_n}{n_2^2 f\,W_2 L_2} = \frac{\rho_n}{f\,W_1 L_1} \cdot (1+\eta_{fl}). \end{equation}\] where \(\eta_{fl}\), given by \[\begin{equation} \eta_{fl} = \left(\frac{G_{ds1}}{n_2\,G_{m1}}\right)^2 \frac{W_1 L_1}{W_2 L_2} \end{equation}\] represents the contribution of the cascode transistor M₂ to the input-referred flicker noise relative to that of M₁. Assuming M₁ and M₂ have the same area and \(G_{m1}/G_{ds1} \gg 1\), the contribution of M₂ to the input-referred flicker noise is negligible compared to that of M₁ and \(\eqref{eqn:p1:Rnf}\) simplifies to \[\begin{equation} R_{nf}(f) \cong \frac{\rho_n}{f\,W_1 L_1}, \end{equation}\] which corresponds to the contribution of M₁ only.

Figure 31: Small-signal schematic of the cascode stage of Figure 25 (a) for the calculation of the noise including the effect of the parasitic capacitance \(C_{p1}\).

Similarly to what was done for the output conductance, the impact of the parasitic capacitance on the noise can be calculated from Figure 31. The output noise conductance is then given by \[\begin{equation} G_{nout} = |H_{n1}(\omega)|^2 \cdot G_{n1} + |H_{n2}(\omega)|^2 \cdot G_{n2}, \end{equation}\] where \[\begin{align} H_{n1}(s) &= \frac{1}{1+s/\omega_p}\\ H_{n2}(s) &= \frac{G_{ds1}}{G_{ms2}} \cdot \frac{1+s/\omega_z}{1+s/\omega_p}. \end{align}\]

Figure 32: Magnitude of the noise transfer functions \(H_{n1}\) and \(H_{n2}\) versus frequency.

The magnitude of \(H_{n1}\) and \(H_{n2}\) versus frequency are sketched in Figure 32. For \(\omega \ll \omega_z \ll \omega_p\), \(H_{n1} \cong 1\) and \(H_{n2} \cong G_{ds1}/G_{ms2}\) which is the result obtained above. However, for \(\omega_z \ll \omega_p \ll \omega\), \(H_{n1} \cong \omega_p/s\) and \(H_{n2} \cong 1\). We see that the cascode effect is lost since the noise of M₂ is no more divided by the cascode gain \(G_{ms2}/G_{ds1}\) but is entirely transferred to the output.

As a conclusion, adding a cascode stage reduces the output conductance without penalty on the noise, but at the cost of a slight voltage overhead for maintaining M₂ in saturation. This is only true for \(\omega < \omega_z = G_{ds1}/C_{p1}\). For frequencies \(\omega \gg \omega_p = G_{ms2}/C_{p1}\) the cascode effect is lost. Note that in order to maximize \(G_{ms2}\) at a given current and minimize its saturation voltage, M₂ should be biased in weak inversion.

Quarto Notebook: Cascode Gain Stage

This Quarto notebook presents an example of cascode design including design and simulation.

7.4.2 Stacked cascode stage

Figure 33: Stacked cascode gain stage.

Can we reduce the output conductance even further without degrading the noise by adding another cascode transistor M₃ on top of the existing cascode as shown in Figure 33? We will check this by first performing a small-signal analysis.

7.4.2.1 Small-signal analysis

Figure 34: Small-signal schematic of the stacked cascode stage of Figure 33 for the calculation of the equivalent transconductance.

The small-signal circuit of the stacked cascode of Figure 33 for the calculation of the equivalent transconductance is shown in Figure 34. The resulting equivalent small-signal transconductance is given by \[\begin{equation} \begin{split} G_{meq} &\triangleq \left.\frac{\Delta I_{out}}{\Delta V_{in}}\right|_{\Delta V_{out}=0}\\ &= G_{m1} \cdot \frac{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})}{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})+G_{ds1}\,(G_{ms3}+G_{ds2}+G_{ds3})} \cong G_{m1}, \end{split} \end{equation}\] which shows that assuming \(G_{ms2},G_{ms3} \gg G_{ds1}, G_{ds2}, G_{ds3}\), like the simple cascode stage, the equivalent transconductance of the stacked cascode stage remains equal to the transconductance of the driver transistor M₁.

Figure 35: Small-signal schematic of the stacked cascode stage of Figure 33 for the calculation of the output conductance.

The output conductance of the stacked cascode stage can be calculated with the help of the small-signal circuit shown in Figure 35. This results in \[\begin{equation} \begin{split} G_{out} &\triangleq \frac{\Delta I_{out}}{\Delta V_{out}}\\ &= \frac{G_{ds1}\,G_{ds2}\,G_{ds3}}{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})+G_{ds1}\,(G_{ms3}+G_{ds2}+G_{ds3})}\\ &\cong G_{ds1}\,\frac{G_{ds2}}{G_{ms2}}\,\frac{G_{ds3}}{G_{ms3}}. \end{split} \end{equation}\] The output conductance is now divided by the square of the self-gain \(G_{ms}/G_{ds}\) instead of the self-gain only for the simple cascode stage. So we can indeed further reduce the output conductance by stacking additional cascode transistors, provided we have enough voltage headroom. However, in a bulk technology, the technique is limited by the additional conductances due to the reverse biased junction at the drain of the top cascode transistor.

The small-signal voltage gain assuming an ideal current source is given by \[\begin{equation} \begin{split} A_v &\triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = -\frac{G_{meq}}{G_{out}} = -\frac{G_{m1}\,(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})}{G_{ds1}\,G_{ds2}\,G_{ds3}}\\ &\cong -\frac{G_{m1}}{G_{ds1}}\,\frac{G_{ms2}}{G_{ds2}}\,\frac{G_{ms3}}{G_{ds3}}. \end{split} \end{equation}\] The voltage gain corresponds roughly to the cascade of three CS stages. The main difference is that it uses the same current for the driver and the cascode transistors.

Does the additional cascode transistor add any penalty in terms of noise? We will check this in the next Section.

7.4.2.2 Noise analysis

Figure 36: Small-signal schematic of the cascode stage of Figure 33 for the noise calculation.

The output noise PSD can be calculated with the help of the schematic shown in Figure 30. The output noise current is then given by \[\begin{equation} \Delta I_{nout} = H_{n1} \cdot I_{n1} + H_{n2} \cdot I_{n2} + H_{n3} \cdot I_{n3}, \end{equation}\] where \[\begin{align} H_{n1} &= \frac{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})}{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})+G_{ds1}\,(G_{ms3}+G_{ds2}+G_{ds3})},\\ H_{n2} &= \frac{G_{ds1}\,(G_{ms3}+G_{ds3})}{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})+G_{ds1}\,(G_{ms3}+G_{ds2}+G_{ds3})},\\ H_{n3} &= \frac{G_{ds1}\,G_{ds2}}{(G_{ms2}+G_{ds2})\,(G_{ms3}+G_{ds3})+G_{ds1}\,(G_{ms3}+G_{ds2}+G_{ds3})}, \end{align}\] which for \(G_{ms2}, G_{ms2} \gg G_{ds1}, G_{ds2}, G_{ds3}\) simplify to \[\begin{align} H_{n1} &\cong 1,\\ H_{n2} &\cong \frac{G_{ds1}}{G_{ms2}},\\ H_{n3} &\cong \frac{G_{ds1}\,G_{ds2}}{G_{ms2}\,G_{ms3}}. \end{align}\] Like the simple cascode, the noise coming from the driver transistor goes directly to the output, the noise coming from the first cascode transistor M₂ is divided by \(G_{ms2}/G_{ds1}\) and the noise coming from the additional cascode transistor M₃ is divided by \(G_{ms2}\,G_{ms3}/(G_{ds1}\,G_{ds2})\). The noise of the additional cacode transistor is therefore completely negligible.

We can conclude that the stacked cascode is a very efficient way to reduce the output conductance and boost the voltage gain without spending more current and without any penalty on noise. It provides the same voltage gain as a cascade of three CS gain stage but at three times less current. Of course, this comes at the cost of more voltage headroom. But if all three transitors are biased in weak inversion their saturation voltage is about \(V_{DSsat} \cong 4\,U_T \cong 120\,mV\) so it requires a minimum of \(360\,mV\) at room temperature, which is acceptable even at low supply voltage. If this voltage is not acceptable, we can use the regulated cascode described in the next Section.

7.4.3 Regulated cascode

Figure 37: Schematic of the regulated cascode [3].

The output conductance can be further reduced by means of the regulated cascode, which schematic is shown in Figure 37 [3]. In this circuit, the gate of the cascode transistor is not connected to a bias voltage source but to the drain of a CS stage implemented by M₃ which has its gate connected to the drain of the driver transitor M₁. Any increase of the output current \(\Delta I_{out}\) leads to an increase of the drain voltage of M₁ and gate voltage of M₃, which reduces the drain voltage of M₃ and gate voltage of M₂, bringing the drain of M₁ back. This feedback loop therefore tends to maintain the drain of M₁ constant, translating into an increase of the output conductance. This is detailed in the small-signal analysis of the next Section.

7.4.3.1 Small-signal analysis

Figure 38: Small-signal schematic of the regulated cascode of Figure 37 for the calculation of the equivalent transconductance.

The small-signal schematic of the regulated cascode of Figure 37 for the calculation of the equivalent transconductance is presented in Figure 38. Solving the KCL equations accounting for all the output conductances leads to the full expression of the equivalent transconductance given by \[\begin{equation} G_{meq} = G_{m1}\cdot\frac{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds2})}{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds2}+G_{ds1})} \end{equation}\] which for \(G_{ms2} > G_{m2} \gg G_{ds2}, G_{ds1}\) reduces to \[\begin{equation} G_{meq} \cong G_{m1}. \end{equation}\] This is the same result as the cascode stage.

Figure 39: Small-signal schematic of the regulated cascode stage of Figure 37 for the calculation of the output conductance.

The small-signal schematic used for the calculation of the output conductance is presented in Figure 39. The output conductance accounting for all transistor’s output conductances is given by \[\begin{equation} G_{out} = G_{ds1} \cdot \frac{G_{ds2}\,G_{ds3}}{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds2}+G_{ds1})}, \end{equation}\] which for \(G_{ms2} > G_{m3}, G_{m2} \gg G_{ds1}, G_{ds2}, G_{ds3}\) reduces to \[\begin{equation}\label{eqn:sol2:gout} G_{out} \cong G_{ds1}\cdot\frac{G_{ds2}}{G_{m2}}\cdot\frac{G_{ds3}}{G_{m3}}. \end{equation}\] Equation \(\eqref{eqn:sol2:gout}\) shows that the output conductance of the regulated cascode is equal to the output conductance of M₁ divided by the square of a transistor self-gain, i.e. \((G_m/G_{ds})^2\), this is \(G_m/G_{ds}\) smaller than that of the simple cascode. It is the same result as the stacked cascode stage, but requires less voltage headroom.

The small-signal voltage gain is given by \[\begin{equation} A_v \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = -\frac{G_{meq}}{G_{out}} = -G_{m1}\cdot\frac{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds2})}{G_{ds1}\,G_{ds2}\,G_{ds3}}, \end{equation}\] which for \(G_{ms2} > G_{m3}, G_{m2} \gg G_{ds2}, G_{ds3}\) reduces to \[\begin{equation}\label{eqn:sol2:av} A_v \cong -\frac{G_{m1}}{G_{ds1}}\cdot\frac{G_{m2}}{G_{ds2}}\cdot\frac{G_{m3}}{G_{ds3}}. \end{equation}\] Equation \(\eqref{eqn:sol2:av}\) shows that the voltage gain of the regulated cascode is equivalent of that of a cascade of three CS stages, i.e. \((G_m/G_{ds})^3\). However, this gain is achieved at lower current since the driver transistor M₁ and the cascode transistor M₂ share the same current (current reuse). It is about equal to the voltage gain of the stacked cascode stage, but again requires less voltage headroom.

We now will perform a noise analysis to investigate what is the impact of the CS transitor M₃ on the noise. This is done in the next Section.

7.4.3.2 Noise analysis

Figure 40: Small-signal schematic of the regulated cascode including the noise sources.

The equivalent small-signal circuit of the regulated cascode including all the noise current sources (except those coming from the bias current sources \(I_{b1}\) and \(I_{b2}\) which are considered ideal) for the calculation of the noise is shown in Figure 40. The output noise current is given by \[\begin{equation} \Delta I_{nout} = H_{n1}\cdot I_{n1} + H_{n2} \cdot I_{n2} + H_{n3} \cdot I_{n3}. \end{equation}\] where \[\begin{align} H_{n1} &= \frac{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds2})}{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds1}+G_{ds2})} \cong 1,\label{eqn:sol2:hn1}\\ H_{n2} &= \frac{G_{ds1}\,G_{ds3}}{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds1}+G_{ds2})} \cong \frac{G_{ds1}\,G_{ds3}}{G_{m2}\,G_{m3}},\label{eqn:sol2:hn2}\\ H_{n3} &= -\frac{G_{m2}\,G_{ds1}}{G_{m2}\,G_{m3}+G_{ds3}\,(G_{ms2}+G_{ds1}+G_{ds2})} \cong -\frac{G_{ds1}}{G_{m3}}.\label{eqn:sol2:hn3} \end{align}\] Equation \(\eqref{eqn:sol2:hn1}\) shows that the noise of M₁ is transferred directly to the output. Equation \(\eqref{eqn:sol2:hn2}\) shows that the noise of M₂ is divided by the square of a transistor self-gain, i.e. divided by \((G_m/G_{ds})^2\). Finally, the noise coming from M₃ is divided by \(G_m/G_{ds}\). This means that the noise coming from M₂ and M₃ are much smaller than the noise coming from M₁ and can usually be neglected. We still will derive the output and input-referred noise accounting for all contributions.

The output noise conductance is given by \[\begin{equation} G_{nout} = |H_{n1}|^2 \cdot G_{n1} + |H_{n2}|^2 \cdot G_{n2} + |H_{n3}|^2 \cdot G_{n3} \end{equation}\] where \(G_{ni}\) is given by \(\eqref{eqn:7:gni}\).

The input-referred noise is obtained by dividing \(G_{nout}\) by \(G_{meq}^2\), resulting in \[\begin{equation} R_{nin} = \frac{G_{nout}(f)}{G_{meq}^2}. \end{equation}\] It can be decomposed into a thermal and flicker noise component according to \[\begin{equation} R_{nin} = R_{nt} + R_{nf}(f) \end{equation}\] \(R_{nt}\) is the total input-referred thermal noise resistance which can be written as \[\begin{equation} R_{nt} = \frac{\gamma_{n1}}{G_{m1}} \cdot (1+\eta_{th}), \end{equation}\] where \(\eta_{th}\) represents the contributions of M₂ and M₃ to \(R_{nt}\) relative to that of M₁ \[\begin{equation}\label{eqn:sol2:etath} \eta_{th} \cong \frac{\gamma_{n2}}{\gamma_{n1}} \cdot \frac{G_{ds1}^2\,G_{ds3}^2}{G_{m1}\,G_{m2}\,G_{m3}^2} + \frac{\gamma_{n3}}{\gamma_{n1}} \cdot \frac{G_{ds1}^2}{G_{m1}\,G_{m3}}. \end{equation}\] \(\eta_{th}\) allows to compare the contributions of M₂ and M₃ to that of M₁. It confirms what we already have mentioned above, namely that the contribution of M₂ (first term in \(\eqref{eqn:sol2:etath}\)) is completely negligible since it is inversely proportional to \((G_m/G_{ds})^4\). The contribution of M₃ (second term in \(\eqref{eqn:sol2:etath}\)) is also very small since it is inversely proportional to \((G_m/G_{ds})^2\).

The input-referred flicker noise resistance is given by \[\begin{equation} R_{nf} = \frac{\rho_n}{f\,W_1\,L_1} \cdot (1 + \eta_{fl}), \end{equation}\] where \(\eta_{fl}\) represents the contributions of M₂ and M₃ to \(R_{nf}\) relative to the that of M₁ \[\begin{equation}\label{eqn:sol2:etafl} \eta_{fl} \cong \left(\frac{G_{ds1}}{G_{m1}} \cdot \frac{G_{ds3}}{G_{m3}}\right)^2 \cdot \frac{W_1\,L_1}{W_2\,L_2} + \left(\frac{G_{ds1}}{G_{m1}}\right)^2 \cdot \frac{W_1\,L_1}{W_3\,L_3}. \end{equation}\] Similarly to the thermal noise, assuming that M₁, M₂ and M₃ have all about the same gate area, \(\eqref{eqn:sol2:etafl}\) shows that the contribution of M₂ (first term in \(\eqref{eqn:sol2:etafl}\)) is completely negligible since it is inversely proportional to \((G_m/G_{ds})^4\). The contribution of M₃ (second term in \(\eqref{eqn:sol2:etafl}\)) is also very small since it is inversely proportional to \((G_m/G_{ds})^2\).

The equivalent noise excess factor of the regulated cascode can then be written as \[\begin{equation}\label{eqn:rc:gammaneq} \gamma_{neq} \triangleq G_{meq} \cdot R_{nt} \cong \gamma_{n1} \cdot (1 + \eta_{th}) \cong \gamma_{n1}. \end{equation}\]

This shows that, similarly to the cascode and stacked gain stages, the noise of the regulated cascode is dominated by the contribution of the driver transistor M₁.

Note

The regulated cascode of Figure 37 achieves about the same performance than the stacked cascode of Figure 33. However we had to add a current branch to bias the CS stage M₃. So we spend more current in the regulated cascode than in the stacked cascode. This claim is not exactly true because in the regulated cascode, the cascode transistor M₂ is self-biased by M₃ and therefore no additional bias circuit is required. This is not true for the stacked cascode which requires at least one additional current branch to bias the cascode transistors M₂ and M₃.

7.4.4 Gain boosting

Figure 41: The principle of gain-boosting [4] [5].

The regulated cascode is a special case of the more general concept of gain boosting illutrated in Figure 41 [4] [5], where the amplifier is implemented by the simple CS source stage M₃ of Figure 37. It has basically the same properties than the regulated cascode except that the gain \(A\) can be made much larger than that of a simple CS stage.

7.4.4.1 Small-signal analysis

Figure 42: Small-signal equivalent circuit used for the calculation of the equivalent transconductance.

Using the small-signal equivalent circuit shown in Figure 42, it is easy to show that the equivalent transconductance of the gain-boosting circuit of Figure 41 is given by \[\begin{equation}\label{eqn:gb:gm} G_{meq} = G_{m1} \cdot \frac{A\,G_{m2}+G_{ms2}+G_{ds2}}{A\,G_{m2}+G_{ms2}+G_{ds1}+G_{ds2}} = G_{m1} \cdot \frac{G_{m2}\,(A+n_2)+G_{ds2}}{G_{m2}\,(A+n_2)+G_{ds1}+G_{ds2}}, \end{equation}\] where we have used \(G_{ms2}=n_2\,G_{m2}\). For \(A \gg n_2\), the output conductances can be neglected \(G_{ds1},G_{ds2} \ll A\,G_{m2}\) and \(\eqref{eqn:gb:gm}\) reduces to \[\begin{equation} G_{meq} \cong G_{m1}. \end{equation}\] Similarly to the cascode and regulated cascode, the equivalent transconductance of the gain boosting circuit is simply equal to the transconductance of the driver transistor M₁.

Figure 43: Small-signal equivalent circuit used for the calculation of the output conductance.

The output conductance can be calculated using the small-signal circuit shown in Figure 43, which leads to \[\begin{equation} G_{out} = \frac{G_{ds1}\,G_{ds2}}{G_{m2}\,(A+n_2)+G_{ds1}+G_{ds2}} \cong \frac{G_{ds1}\,G_{ds2}}{G_{m2}\,(A+n_2)} \cong G_{ds1} \cdot \frac{G_{ds2}}{G_{m2}} \cdot \frac{1}{A}, \end{equation}\] which corresponds to the output conductance of the regulated cascode in case \(A=G_{m3}/G_{ds3}\), but can be made smaller with a larger amplifier gain \(A\). It can therefore be made arbritarly small.

Figure 44: Small-signal equivalent circuit used for the calculation of the voltage gain.

The voltage gain can be calculated with the help of the schematic shown in Figure 44 resulting in \[\begin{equation} A_v = -\frac{G_{m1}\,(G_{ds2}+G_{m2}\,(A+n_2))}{G_{ds1}\,G_{ds2}} = -\frac{G_{m1}}{G_{ds1}} \cdot \left(\frac{G_{m2}}{G_{ds2}} \cdot (A+n_2)+1\right), \end{equation}\] which for \(A \gg n_2\) simplifies to \[\begin{equation}\label{eqn:Av:gb} A_v \cong -\frac{G_{m1}}{G_{ds1}} \cdot \frac{G_{m2}}{G_{ds2}} \cdot A. \end{equation}\] Equation \(\eqref{eqn:Av:gb}\) corresponds to the voltage gain of the regulated cascode in case \(A=G_{m3}/G_{ds3}\), but can be made larger with a larger amplifier gain \(A\).

7.4.4.2 Noise analysis

Figure 45: Small-signal equivalent circuit used for the calculation of the noise.

The noise can be analyzed by means of the small-signal circuit shown in Figure 45 where \(V_{noa}\) represents the input-referred noise voltage of the amplifier. It is then easy to show that the input-referred noise resistance of the gain boosting circuit is given by \[\begin{equation}\label{eqn:gb:rnin} R_{nin} \cong \frac{G_{n1}}{G_{m1}^2} + \left(\frac{G_{ds1}}{A\,G_{m1}\,G_{m2}}\right)^2 \cdot G_{n2} + \left(\frac{G_{ds1}}{G_{m1}}\right)^2 \cdot R_{noa}, \end{equation}\] where \(R_{noa}\) is the amplifier equivalent input-referred noise resistance. Similarly to the regulated cascode, the noise of the cascode transistor M₂ is divided by the square of the gain \(A\,G_{m1}/G_{ds1}\) and can therefore be completely neglected. The impact of the noise coming from the amplifier depends very much on how this amplifier is implemented. If we want to make its contribution corresponding to the last term in \(\eqref{eqn:gb:rnin}\) smaller than the contribution of M₁, we need to have \[\begin{equation}\label{eqn:gb:rnoa} \frac{G_{n1}}{G_{ds1}^2} > R_{noa}. \end{equation}\] If we only consider the thermal noise, then \(G_{n1} = \gamma_{n1}\,G_{m1}\) and \(R_{oa} = \gamma_{noa}/G_{moa}\) and \(\eqref{eqn:gb:rnoa}\) becomes \[\begin{equation} \gamma_{noa} < \gamma_{n1}\,\frac{G_{m1}\,G_{moa}}{G_{ds1}^2} \end{equation}\] which should not be too difficult to achieve assuming the gain of the driver \(G_{m1}/G_{ds1}\) is large enough.

7.4.4.3 Summary

Cascoding is an efficient way to increase the output resistance and the voltage gain without spending more current and without degrading the noise at the cost of a slightly reduced output voltage swing. A simple cascode stage achieves the same gain as the cascade of two CS stages, but with less current and less noise.

The output resitance and voltage gain can be further increased by stacking an additional cascode transistor. The output conductance is divided by the square of the self-gain \(G_{ms}/G_{ds}\). The stacked cascode achieves a voltage gain that is better than the cascade of three CS stages with less current and less noise. Although this reduces the output voltage swing, if all the stacked transistors are ibiased in weak inversion we only loose about \(120\,mV\) for the additional cascode transistor.

To avoid loosing an additional saturation voltage, we can use the regulated cascode which gives about the same results as the stacked cascode.

Finally, the regulated cascode can be further improved by replacing the CS stage in the loop by a full amplifier. Of course this comes at the cost of more power consumption.

7.4.5 Pseudo cascode or “Poor man’s cascode”

(a) Schematic.

(b) Small-signal schematic.

Figure 46: Pseudo cascode or “poor man’s cascode”.

As shown in Section 7.4.6, cascode transistors usually require one or more additional bias strings to be properly biased. The current in these bias strings is wasted and add up to the current consumption. As shown in Figure 46 (a), we can avoid using an additonal bias string by connecting the gate of the cascode transistor M₂ to the gate of the driver transistor M₁. Since M₁ and M₂ have now the same gate voltage, \(V_{D1} < V_{DSsat1}\) which means that M₁ is actually biased in the linear region. Its drain transconductance can no more be neglected and needs to be accounted for in the small-signal schematic shown in Figure 46 (b). The cascode output conductance assuming that M₂ is in saturation is given by \[\begin{equation}\label{eqn:pmc_Gout1} \begin{split} G_{out} &\triangleq \frac{\Delta I_o}{\Delta V_o} = G_{ds2} \, \frac{G_{ds1}+G_{md1}}{G_{ms2}+G_{md1}+G_{ds1}+G_{ds2}}\\ &\cong G_{ds2}\,\frac{G_{ds1}+G_{md1}}{G_{ms2}+G_{md1}} = G_{ds2}\,\frac{G_{ds1}/G_{ms2}+G_{md1}/G_{ms2}}{1+G_{md1}/G_{ms2}}, \end{split} \end{equation}\] where we have assumed that \(G_{ms2} \gg G_{ds1},G_{ds2}\).

Figure 47: Inversion charge versus channel voltage for M₁ and M₂.

Since M₁ and M₂ share the same gate voltage, they have the same pinch-off voltage \(V_P\) and the same \(Q_i/C_{ox}\) versus channel voltage \(V\) as illustrated in Figure 47, where the blue area corresponds to \(I_b/\beta_1\) and the red area to \(I_b/\beta_2\). Since the drain voltage of M₁ is equal to the source voltage of M₂ \(V_{D1}=V_{S2}\) we have \[\begin{equation} \frac{G_{md1}}{\beta_1} = \frac{G_{ms2}}{\beta_2}. \end{equation}\] The drain transconductance \(G_{md1}\) of M₁ is therefore related to the source transcondcutance \(G_{ms2}\) of M₂ according to \[\begin{equation}\label{eqn:pmc_Gmd1_Gms2} \frac{G_{md1}}{G_{ms2}} = \frac{\beta_1}{\beta_2}. \end{equation}\] We can replace \(G_{md1}/G_{md2}\) in \(\eqref{eqn:pmc_Gout1}\) by \(\eqref{eqn:pmc_Gmd1_Gms2}\) resulting in \[\begin{equation}\label{eqn:pmc_Gout2} G_{out} \cong G_{ds2}\,\frac{G_{ds1}/G_{ms2}+\beta_1/\beta_2}{1+\beta_1/\beta_2}. \end{equation}\] We see that for \(\beta_1/\beta_2 \rightarrow 0\) \[\begin{equation} G_{out} \rightarrow \frac{G_{ds1}}{G_{ms2}/G_{ds2}} \end{equation}\] which is identical to the result we obtained for the normal cascode stage. We can therefore reduce \(G_{out}\) by making M₂ much wider than M₁ and by decreasing \(\beta_1\) by making M₁ longer than M₂. This allows to assume that \(\beta_2 \gg \beta_1\), resulting in \[\begin{equation}\label{eqn:pmc_Gout3} G_{out} \cong G_{ds2} \cdot \left(\frac{G_{ds1}}{G_{ms2}} + \frac{\beta_1}{\beta_2}\right). \end{equation}\] The first term in the brackets of \(\eqref{eqn:pmc_Gout2}\) corresponds to the inverse of the conductance reduction of the normal cascode while the second term can be considered much smaller than 1.

Note that the above analysis is valid in any mode of inversion. However in weak inversion we can take advantage of short-channel effects that will change the threshold voltage compared to its long-channel value. Indeed, in weak inversion, the drain current writes \[\begin{equation} I_D = I_{spec}\,e^{\frac{V_G-V_{T0}}{n\,U_T}}\,\left(e^{-\frac{V_S}{U_T}}-e^{-\frac{V_D}{U_T}}\right) \end{equation}\] and the source and drain transconducdantes are given by \[\begin{equation} G_{ms(d)} = G_{spec}\,e^{\frac{V_G-V_{T0}}{n\,U_T}}\,e^{-\frac{V_S(D)}{U_T}}. \end{equation}\] The \(G_{md1}/G_{ms2}\) ratio is then given by \[\begin{equation}\label{eqn:pmc_Gmd1_Gms2_wi} \frac{G_{md1}}{G_{ms2}} = \frac{I_{spec1}}{I_{spec2}}\,e^{\frac{V_{T02}-V_{T01}}{n\,U_T}} = \frac{\beta_1}{\beta_2}\,e^{-\frac{\Delta V_{T0}}{n\,U_T}} \end{equation}\] where \(\Delta V_{T0} \triangleq V_{T01}-V_{T02}\). The \(\beta_1/\beta_2\) ratio appearing in \(\eqref{eqn:pmc_Gout2}\) needs to be replaced by \(\eqref{eqn:pmc_Gmd1_Gms2_wi}\). We can take advantage of the reduction of the threshold voltage with the length due to short-channel effects. Therefore, taking \(L_2=L_{min}\) will make the threshold of M₂ smaller than that of M₁ because of short-channel effects resulting in \(\Delta V_{T0} > 0\). If \(\Delta V_{T0} > n\,U_T\), we then don’t need to make \(\beta_2 \gg \beta_1\). It can even work with \(\beta_2 = \beta_1\)!

7.4.6 Low-voltage cascode biasing

Figure 48: Schematic of a simple cascode stage with its biasing string.

The schematic of Figure 48 shows a cascode stage M₁ and M₂, with an additional bias string. M₁ is the driver transistor, M₂ the cascode transistor and M₃ the additional transistor used to bias the cascode transistor M₂. For low-voltage operation we need to set the cascode gate voltage such that the drain voltage \(V_{D1}\) of the driver transistor is at the edge of saturation.

We start with the analysis assuming that the transistors are all biased in strong inversion.

7.4.6.1 In strong inversion

In strong inversion, the saturation voltage is given by \(V_{Dsat1} = V_{P1}\). This means that we need to set \(V_{D1}\) to \(V_{P1}\). We are assuming that all transistors are biased in saturation. Since all transistor are biased at the same current \(I_b\), we can write \[\begin{align} \frac{\beta_1\,n_1}{2}\,V_{P1}^2 &= \frac{\beta_2\,n_2}{2}\,(V_{P2}-V_{D1})^2,\label{eqn:id1_id2_1}\\ \frac{\beta_3\,n_3}{2}\,V_{P3}^2 &= \frac{\beta_2\,n_2}{2}\,(V_{P2}-V_{D1})^2.\label{eqn:id3_id2_1} \end{align}\] Since M₂ and M₃ share the same gate they have the same pinch-off voltage \(V_{P3}=V_{P2}\). Also we want \(V_{D1}=V_{P1}\). Defining \(P \triangleq \beta_2/\beta_3\) and \(K \triangleq \beta_2/\beta_1\). Replacing in \(\eqref{eqn:id1_id2_1}\) and \(\eqref{eqn:id3_id2_1}\) results in \[\begin{align} n_1\,V_{P1}^2 &= K\,n_2\,(V_{P2}-V_{P1})^2,\label{eqn:id1_id2_2}\\ n_3\,V_{P2}^2 &= P\,n_2\,(V_{P2}-V_{P1})^2.\label{eqn:id3_id2_2} \end{align}\] Solving \(\eqref{eqn:id3_id2_2}\) for \(V_{P2}\) results in \[\begin{equation} V_{P2} = \frac{V_{P1}}{1-\sqrt{\frac{n_3}{n_2\,P}}} = \frac{V_{P1}}{1-\frac{1}{1+\sqrt{n_2/n_1\,K}}}, \end{equation}\] which for \(n_1=n_2=n_3=n\) simplifies to \[\begin{equation} V_{P2} \cong \left(1+\frac{1}{\sqrt{K}}\right)\,V_{P1}. \end{equation}\] The drain-to-source saturation \(V_{DSsat2}\) of M₂ is given by \[\begin{equation} V_{DSsat2} = V_{P2}-V_{S2} = V_{P2}-V_{P1} \cong \frac{V_{P1}}{\sqrt{K}} \end{equation}\] which is \(\sqrt{K}\) lower than \(V_{Dsat1}=V_{P1}\). The minimum output voltage at the drain of M₂ keeping both M₁ and M₂ in saturation is therefore \[\begin{equation} V_{D2,min} = V_{Dsat1} + V_{DSsat2} \cong V_{P1} + V_{P2} - V_{P1} = V_{P2}. \end{equation}\] The ratio \(P\) required to size M₃ is then obtained by solving \(\eqref{eqn:id3_id2_2}\) for \(P\) resulting in \[\begin{equation} P = \frac{n_3}{n_2}\,\left(1+\sqrt{\frac{n_2}{n_1}\,K}\right)^2, \end{equation}\] which for \(n_1=n_2=n_3=n\) simplifies to \[\begin{equation} P \cong \left(1+\sqrt{K}\right)^2. \end{equation}\]

Choosing \(K=1\) makes the drain-to-source saturation voltages of M₁ and M₂ equal. Indeed, if we set \(K=1\) (i.e. \(\beta_2=\beta_1\)) then \(P=4\) (i.e. \(\beta_2=4\,\beta_3\)) and \(V_{P2} = 2\,V_{P1}\) [6]. The drain-to-source saturation voltage of M₂ \(V_{DSsat2}\) is then equal to the drain saturation voltage of M₁ \(V_{DSsat2} \cong V_{Dsat1} \cong V_{P1}\) [6]. The minimum voltage at the drain of M₂ is therefore \(V_{D2,min} = 2\,V_{P1}\).

We can make the minimum output voltage even lower by making M₂ much larger than M₁. then \(K \gg 1\) and \(V_{P2} \cong V_{P1}\). Note that this increases the parasitic capacitance at the cascode node (source of M₂). Note that this result is valid for all levels of inversion.

7.4.6.2 In weak inversion

(a) Principle.

(b) Detailed schematic.

Figure 49: Low-voltage cascode biasing in weak inversion.

In weak inversion, we need to set the drain voltage \(V_{D1}\) to the saturation voltage in weak inversion which is just a few \(U_T\) (typically \(4\,U_T\)). To do this we need that the bias voltage source \(V_b\) shown in Figure 49 (a) is a PTAT voltage equal to a few \(U_T\) [7] [8].

The voltage source \(V_b\) can be implemented as shown in Figure 49 (b) by transistors M₄ and M₅. We assume that all transistors are biased in weak inversion \[\begin{align} I_{D3} &= 2 n_3\,\beta_3\,U_T^2\,e^{\frac{V_{P3}-V_{D5}}{U_T}},\\ I_{D4} &= 2 n_4\,\beta_4\,U_T^2\,e^{\frac{V_{P4}-V_{D5}}{U_T}},\\ I_{D5} &= 2 n_5\,\beta_5\,U_T^2\,e^{\frac{V_{P5}}{U_T}}\,\left[1-e^{-\frac{V_{D5}}{U_T}}\right]. \end{align}\]

Since M₄ and M₅ share the same gate, they have the same pinch-off voltage \(V_{P4}=V_{P5}\). Since \(I_{D3}=I_{D4}=I_b\), we have \(I_{D5} = I_{D3}+I_{D4} = 2I_{D4}\) resulting in \[\begin{equation}\label{eqn:id5_id4} n_5\,\left[1-e^{-\frac{V_{D5}}{U_T}}\right] = 2 n_4\,M\,e^{-\frac{V_{D5}}{U_T}} \end{equation}\] with \(M \triangleq \beta_4/\beta_5\). Solving \(\eqref{eqn:id5_id4}\) for \(V_{D5}\) results in \[\begin{equation} V_{D5} = U_T\,\ln\left(1+2\frac{n_4}{n_5}\,M\right) \cong U_T\,\ln\left(1+2\,M\right). \end{equation}\]

Since M₂ and M₃ are biased at the same current \(I_b\) we can write \(I_{D2}=I_{D3}\) resulting in \[\begin{equation}\label{eqn:id2_id3} n_2\,P\,e^{\frac{-V_{D1}}{U_T}} = n_3\,e^{\frac{-V_{D5}}{U_T}}. \end{equation}\] with \(P \triangleq \beta_2/\beta_3\).

Solving \(\eqref{eqn:id2_id3}\) for \(V_{D1}\), we get \[\begin{equation} V_{D1} = U_T\,\ln\left[\frac{n_2}{n_3}\,P\,\left(2\frac{n_4}{n_5}\,M\right)\right] \cong U_T\,\ln[P\,(1+2M)]. \end{equation}\]

Choosing \(P=M=8\) results in \(V_{D1} =\) 4.913 \(U_T\) or 127 \(mV\) at room temperature. The minimum voltage at the drain of M₂ keeping both M₁ and M₂ in saturation is then equal to \(V_{D2,min} =\) 9.825 \(U_T\) or 254 \(mV\) at room temperature.

7.4.6.3 In all modes of inversion

Figure 50: Schematic of a simple cascode stage with its biasing string valid in all modes of inversion.

The bias techniques presented above apply to weak and strong inversion. We can reuse the circuit of Figure 49 (b) to implement a biasing technique that is valid in any modes of inversion. The latter is based on imposing a certain \(I_R/I_F=i_r/i_f\) ratio. Indeed, the \(i_r/i_f\) ratio can be used as a criteria to define whether a transistor is in saturation. The output characteristic defined as \(i_d/i_f = (i_f-i_r)/i_r = 1-i_r/i_f\) is plotted versus \(v_{ds}\) for different values of \(i_f\) (hence of \(v_p-v_s\)) in Figure 51.

Figure 51: Normalized drain current \(i_d/i_f\) versus normalized drain-to-source voltage \(v_{ds}\).

Figure 52: \(i_r/i_f\) ratio versus the normalized drain-to-source voltage \(v_{ds}\) for different values of \(i_f\).

Figure 51 shows how the saturation voltage is actually decreasing when moving from strong to weak inversion where it is only a few \(U_T\) (typically \(4\,U_T\)). The \(i_r/i_f\) ratio is also plotted versus \(v_{ds}\) for different values of \(i_f\) in Figure 52. The saturation voltage can be defined as the \(v_{ds}\) voltage corresponding to a certain \(i_r/i_f\) ratio as shown by the intersections of the curves with the horizontal dashed black line corresponding to \(i_r/i_f=0.02\). Using this criteria we can plot in Figure 53 the normalized saturation voltage \(v_{dssat}\) versus \(i_f\) for different values of the \(i_r/i_f\) ratio. We clearly see how the saturation voltage saturates to a few \(U_T\) in weak inversion and tends to \(v_p-v_s\) (corresponding to the black dashed line) in strong inversion for very small values of the \(i_r/i_f\) ratio (ideally zero).

Figure 53: Normalized saturation voltage verus \(i_f\) for different values of the \(i_r/i_f\) ratio.

As shown in Figure 52, if a transistor is not fully saturated, for a given \(v_{ds}\) voltage we get a certain \(i_r/i_f\) ratio. So if two transistors that are not fully saturated have the same \(V_{DS}\) voltage, they also have the same \(I_R/I_F\) ratio (or \(i_r/i_f\) ratio).

Let’s now come back to the circuit of Figure 50 for which we define \(K \triangleq \beta_2/\beta_1\) and \(M \triangleq \beta_4/\beta_5\). Additionally we set \(\beta_2/\beta_3=\beta_5/\beta_1=1\).

Assuming that M₂ is in saturation, since M₂ and M₃ have the same \(\beta\), i.e. the same specific current \(I_{spec}\), they also have the same forward currents \(I_{F2}=I_{F3}\) [9]. Since M₂ and M₃ also have the same gate voltage, they also have the same pinch-off voltages \(V_{P2}=V_{P3}\). In order to have \(I_{F2}=I_{F3}\) with \(V_{P2}=V_{P3}\) requires \(V_{S2}=V_{S3}\) and hence \(V_{D1} = V_{D5}\) [9].

Transistors M₁ and M₅ are actually not fully saturated, but, as discussed above, since they have the same \(V_{DS}\) voltage they also have the same \(I_R/I_F\) ratio \[\begin{equation} \frac{I_{R1}}{I_{F1}} = \frac{I_{R5}}{I_{F5}}. \end{equation}\]

Since M₄ and M₅ share the same gate, they have the same pinch-off voltage. Since the source voltage of M₄ \(V_{S4}\) (or its normalized form \(v_{s4}\)) is equal to the drain voltage of M₅ \(V_{D5}\) (or its normalized form \(v_{d5}\)), we can write \(i_{f4} = i_{r5}\), because \(i_f\) and \(i_r\) are the same function \(f(v)\) of the normalized voltage \(v\), with \(v=v_p-v_s\) for \(i_f\) and \(v=v_p-v_d\) for \(i_r\) [10] [9]. We can then write \[\begin{equation} \frac{I_{F4}}{I_{spec4}} = \frac{I_{R5}}{I_{spec5}}. \end{equation}\] Since \(\beta_4/\beta_5 = I_{spec4}/I_{spec5} = M\), we get \[\begin{equation} I_{F4} = \frac{I_{spec4}}{I_{spec5}}\,I_{R5} = M \cdot I_{R5}. \end{equation}\] Current \(I_{F4}\) is also equal to \(I_b/N\) and hence \[\begin{equation} I_{R5} = \frac{I_b}{M \cdot N}. \end{equation}\]

Writing the Kirchhoff’s current law at the drain node of M₅ gives \[\begin{equation}\label{eqn:id5} I_{D5} = I_{F5}\,\left(1 + \frac{I_{R5}}{I_{F5}}\right) = \left(1 + \frac{1}{N}\right)\,I_b. \end{equation}\] Assuming that M₅ is close to saturation, we can assume that \(I_{R5}/I_{F5} \ll1\) and \(\eqref{eqn:id5}\) rewrites \[\begin{equation} I_{F5} \cong \left(1 + \frac{1}{N}\right)\,I_b. \end{equation}\]

The \(I_{F1}/I_{R1}\) ratio for M₁ is finally given by [9] \[\begin{equation} \frac{I_{F1}}{I_{R1}} = \frac{I_{F5}}{I_{R5}} \cong M \cdot (N+1), \end{equation}\] which turns out to be independent of the bias current \(I_b\).

Which value of \(I_{F1}/I_{R1}\) should we choose? One criteria is to choose \(M \cdot (N+1)\) such that the drain transconductance of M₁ \(G_{md1}\) becomes smaller than its output conductance \(G_{ds1}\). If M₁ is not biased too much in strong inversion, then \(G_{md1}\) can be approximated by \[\begin{equation} G_{md1} \cong \frac{I_{R1}}{U_T}. \end{equation}\] The output conductance can be written as \[\begin{equation}\label{eqn:} G_{ds1} \cong \frac{I_{F1}}{V_{M1}}, \end{equation}\] where \(V_{M1} \cong \lambda \cdot L_{eff1}\) is the channel-length modulation voltage.

We can then write \[\begin{equation} M \cdot (N+1) = \frac{I_{F1}}{I_{R1}} > \frac{V_{M1}}{U_T}. \end{equation}\]

Quarto Notebook: Low-voltage Cascode Biasing Techniques

This notebook presents the low-voltage cascode biasing technique for all modes of inversion discussed above and applies it to the design of a low-voltage cascode current mirror (LVCCM). The notebook includes the design and the validation by simulations.

7.5 Voltage followers (common-drain stages)

7.5.1 Simple voltage-follower (SVF)

7.5.1.1 In common substrate

7.5.1.1.1 Large-signal analysis

(a) Schematic.

(b) Large-signal transfer characteristic.

Figure 54: Voltage-follower in common substrate.

The last basic gain-cell is the common-drain stage or voltage follower, also called source-follower, shown in Figure 54 (a) [11]. In this implementation the voltage follower transistor M₁ is in the common substrate and biased by a current source M₂. Since the bias current remains constant, the \(V_{GS}\) voltage of M₁ also remains about constant. This means that when we sweep the input voltage, the output voltage will follow with a shift about equal to \(V_{DSsat2}+V_{T0}\) as shown in the large-signal transfer characteristic of Figure 54 (b). Now, the slope of the large-signal transfer characteristic is not exactly equal to unity. This is due to the fact that the source voltage of M₁ does not change in exactly the same way the gate voltage does because of the substrate or body effect. The voltage follower is an example of circuit that can be better analyzed using the source-referred current model. With this model the drain current of M₁ in strong inversion and saturation (assuming a long-channel transistor) is given by \[\begin{equation} I_{D1} = I_b = \frac{\beta_1}{2 n_1}\,(V_{GS1}-V_{T1})^2 \end{equation}\] with \(V_{T1} = V_{T0n} + (n_1-1)\,V_{S1} = V_{T0n} + (n_1-1)\,V_{out}\). The \(V_{GS1}\) voltage is then given by \[\begin{equation} V_{GS1} = V_{T1} + \sqrt{\frac{2 n_1\,I_b}{\beta_1}} \end{equation}\] and the output voltage \(V_{out}\) writes \[\begin{equation}\label{eqn:voltage_follower_vo1} V_{out} = V_{in} - V_{GS1} = V_{in} - V_{T1} - \sqrt{\frac{2 n_1\,I_b}{\beta_1}}. \end{equation}\] where \(V_{T1}\) depends on \(V_{out}\). Solving for \(V_{out}\) results in \[\begin{equation}\label{eqn:voltage_follower_vo2} V_{out} = \frac{V_{in}-V_{T0n}}{n_1} - \sqrt{\frac{2 I_b}{n_1\,\beta_1}}. \end{equation}\] Since the bias current is constant, the last term in \(\eqref{eqn:voltage_follower_vo2}\) also remains constant. The output voltage \(V_{out}\) then follows the input voltage but with a slope \(1/n_1\) instead of 1.

We will see below that this drawback can be corrected by putting M₁ into a separate well as shown in Figure 57 (a).

We can obtain the voltage gain from the following small-signal analysis.

7.5.1.1.2 Small-signal analysis

(a) For voltage gain calculation.

(b) For output conductance calculation.

Figure 55: Small-signal schematics of the source follower in common substrate.

The small-signal circuit of the voltage follower of Figure 54 (a) ignoring the load capacitance \(C_L\), is shown in Figure 55 where \(G_o = G_{ds1}+G_{ds2}\) includes the output conductances of M₁ and M₂. The source transconductance \(G_{ms1}\) is controlled by the output voltage and therefore adds to the output conductance. It is straightforward to derive the DC small-signal voltage gain as \[\begin{equation} A_{dc} = \frac{G_{m1}}{G_{ms1}+G_o} = \frac{G_{m1}}{G_{ms1}+G_{ds1}+G_{ds2}} \cong \frac{G_{m1}}{G_{ms1}} = \frac{1}{n_1} < 1, \end{equation}\] where \(G_{ms1} =n_1\,G_{m1} \gg G_{ds1}, G_{ds2}\). This is consistent with the above large-signal analysis and explains why the voltage gain is smaller than unity. The voltage-follower is actually loaded by its own source transconductance \(G_{ms1}\) which is \(n_1\) times larger than the gate transcondcutrance \(G_{m1}\).

The output conductance can be derived with the help of Figure 55 (b) resulting in \[\begin{equation} G_{out} = G_{ms1}+G_{ds1}+G_{ds2} \cong G_{ms1}. \end{equation}\] The source follower offers a high output conductance (low output resistance). This is why it is sometimes used as an output stage in simple OPAMPs [12].

The voltage gain accounting for the load capacitance \(C_L\) is given by \[\begin{equation} A_v \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = \frac{A_{dc}}{1 + s/\omega_c} \end{equation}\] where \[\begin{align} A_{dc} &= \frac{G_{m1}}{G_{ms1} + G_o} \cong \frac{G_{m1}}{G_{ms1}} = \frac{1}{n_1},\\ \omega_c &= \frac{G_{ms1} + G_o}{C_L} \cong \frac{G_{ms1}}{C_L}. \end{align}\] The source-follower bandwidth is therefore \(\omega_c \cong G_{ms1}/C_L\).

7.5.1.1.3 Noise analysis

Figure 56: Small-signal schematic used for the noise analysis.

The noise analysis can be performed with the help of the small-signal schematic shown in Figure 56 where the small-signal input voltage has been set to zero and where \(I_n=I_{n1}+I_{n2}\) accounts for the noise coming from both M₁ and M₂. The output noise voltage is given by \[\begin{equation} V_{nout} = R_{mn}(s)\cdot I_n, \end{equation}\] where \[\begin{equation}\label{eqn:vf:rmn} R_{mn}(s) = -\frac{1/G_{ms1}}{1+s/\omega_c} \end{equation}\] with \(\omega_c = G_{ms1}/C_L\) the cut-off frequency. The output noise resistance for \(\omega \ll \omega_c = G_{ms1}/C_L\) and assuming that \(G_{ms1} \gg G_o = G_{ds1}+G_{ds2}\) is given by \[\begin{equation} R_{nout} = |R_{mn}(\omega)|^2 \cdot (G_{n1}+G_{n2}) \cong |R_{mn}(0)|^2 \cdot (G_{n1}+G_{n2}) = \frac{G_{n1}+G_{n2}}{G_{ms1}^2} \end{equation}\] where \(G_{n1}\) and \(G_{n2}\) are the noise conductances at the drain of M₁ and M₂ including both the thermal and flicker noise and given by \(\eqref{eqn:7:gni}\).

The input-referred noise resistance is then given by \[\begin{equation}\label{eqn:sf1_rnin} R_{nin} = R_{nt} + R_{nf} = \frac{R_{nout}}{A_{dc}^2} = \frac{G_{n1}}{G_{m1}^2}\,(1+\eta) \end{equation}\] where \[\begin{equation} \eta = \frac{G_{n2}}{G_{n1}} \end{equation}\] represents the contribution of M₂ to the input-referred noise relative to that of M₁.

The thermal noise input-referred noise resistance \(R_{nt}\) is given by \[\begin{equation} R_{nt} = \frac{\gamma_{n1}}{G_{m1}}\,(1+\eta_{th}), \end{equation}\] with \[\begin{equation} \eta_{th} = \frac{\gamma_{n2}}{\gamma_{n1}}\,\frac{G_{m2}}{G_{m1}}. \end{equation}\] In order to minimize the contribution of M₂ to the input-referred noise, we should make \(G_{m2}/G_{m1}\) as small as possible. To this purpose we should bias the voltage follower M₁ in weak inversion and the bias current source M₂ as much in strong inversion as the voltage headroom allows for. Unfortunately this is not always possible because we usually also want to have a small output resistance and hence a large \(G_{m1}\). Under this constraint it becomes hard to bias M₁ in weak inversion without prohibitively increasing its gate area and related parasitic capacitances.

We can calculate the output thermal noise voltage accounting for the low-pass transfer function given by \(\eqref{eqn:vf:rmn}\). The equivalent noise bandwidth is \(B_n=\pi/2\,f_c=\omega_c/4=G_{ms1}/(4\,C_L)\). Without surprise, the variance of the output thermal noise voltage is proportional to \(k_B\,T/C_L\) because the noise bandwidth and the white noise level are proportional to and inversely proportional to \(G_{m1}\) resulting in \[\begin{equation} \begin{split} V_{nout}^2 &= R_{mn}(0)^2\,B_n\,S_{nout} = \frac{1}{G_{ms1}^2}\,\frac{G_{ms1}}{4\,C_L}\,4\,k_B\,T\,\gamma_{n1}\,G_{m1}\,(1+\eta_{th})\\ &= \frac{k_B\,T}{C_L}\,\frac{G_{m1}}{G_{ms1}}\,\gamma_{n1}\,(1+\eta_{th}) = \frac{k_B\,T}{C_L}\,\delta_{n1}\,(1+\eta_{th}), \end{split} \end{equation}\] where \(\delta_{n1}\) is equal to \(1/2\) for M₁ in WI and \(2/3\) for M₁ in SI.

7.5.1.2 In separate well

7.5.1.2.1 Large-signal analysis

(a) Schematic.

(b) Large-signal transfer characteristic.

Figure 57: Source follower in separate well.

In this case the source-to-bulk voltage of M₁ is actually zero turning of its source transconductance. The output voltage is given by \(\eqref{eqn:voltage_follower_vo1}\) but with \(V_{T1} =V_{T0n}\) \[\begin{equation} V_{out} = V_{in} - V_{GS1} = V_{in} - V_{T0n} - \sqrt{\frac{2 n_1\,I_b}{\beta_1}}. \end{equation}\] The output voltage now follows the input voltage with a unity gain as shown in Figure 57 (b).

7.5.1.2.2 Small-signal analysis

(a) For voltage gain and noise calculation.

(b) For output conductance calculation.

Figure 58: Small-signal schematics of the source follower in separate well.

The DC small-signal voltage gain of the voltage follower in separate well can be derived with the help of Figure 58 (a) resulting in \[\begin{equation} A_{v0} = \frac{G_{m1}}{G_{m1}+G_{ds1}+G_{ds2}} \cong 1. \end{equation}\] As mentioned in the large-signal analysis, the DC small-signal voltage gain is now equal to unity, assuming that \(G_{m1} \gg G_{ds1}, G_{ds2}\).

The output conductance is now equal to \(G_{m1}\) \[\begin{equation} G_{out} = G_{m1}+G_{ds1}+G_{ds2} \cong G_{m1}. \end{equation}\]

The transfer function accounting for the load capacitance \(C_L\) is given by \[\begin{equation} A_v \triangleq \frac{V_{out}}{V_{in}} = \frac{A_{dc}}{1 + s/\omega_c} \end{equation}\] where \[\begin{align} A_{dc} &= \frac{1}{1 + G_o/G_{m1}} \cong 1,\\ \omega_c &= \frac{G_{m1} + G_o}{C_L} \cong \frac{G_{m1}}{C_L}. \end{align}\] The bandwidth is now \(\omega_c \cong G_{m1}/C_L\), which is \(n\)-times smaller compared to the case where M₁ is in a common-substrate.

7.5.1.2.3 Noise analysis

Figure 59: Small-signal schematic used for the noise analysis.

The noise analysis is similar to that of the voltage follower in a common substrate. The transresistance is given by \[\begin{equation} R_{mn} = -\frac{1/G_{m1}}{1+s/\omega_c} \end{equation}\] where \(\omega_c = G_{m1}/C_L\) is the cut-off frequency. The output noise resistance for \(\omega \ll \omega_c = G_{m1}/C_L\) and assuming that \(G_{m1} \gg G_o = G_{ds1}+G_{ds2}\) is given by \[\begin{equation} R_{nout} = |R_{mn}(\omega)|^2 \cdot (G_{n1}+G_{n2}) \cong |R_{mn}(0)|^2 \cdot (G_{n1}+G_{n2}) = \frac{G_{n1}+G_{n2}}{G_{m1}^2}. \end{equation}\] The input-referred noise resistance is actually identical to \(\eqref{eqn:sf1_rnin}\) with \(A_{dc}=1\).

The output thermal noise voltage variance is given by \[\begin{equation} V_{nout}^2 = R_{mn}(0)^2\,B_n\,S_{nout} = \frac{1}{G_{m1}^2}\,\frac{\omega_c}{4}\,4\,k_B\,T\,\gamma_{n1}\,G_{m1}\,(1+\eta_{th}) = \frac{k_B\,T}{C_L}\,\gamma_{n1}\,(1+\eta_{th}). \end{equation}\]

7.5.2 The super source-follower (SSF)

Figure 60: The super source-follower (SSF) [13] [14]

The output resistance of the SVF is limited to \(1/G_m\) and might need a high current consumption to have a sufficiently low resistance. This can be circumvented by using the super soource follower (SSF) shown in Figure 60 [13] [14]. The SSF introduces a feedback loop with an additional pMOS common-source transistor M₂. The feedback loop operates as follows. Let’s assume that the ouput voltage increases. For a constant input voltage, the drain current of M₁ decreases and its drain voltage and hence gate voltage of M₂ increases. The drain current of M₂ also decreases and so does its drain voltage bringing the output voltage back to its quiescent value. This means that the feedback loop is trying to keep the output voltage constant, independently of the output current, resulting in a high output resistance. This feature will be analyzed in more details in the next Section.

7.5.2.1 Output resistance

Figure 61: Small-signal schematic of the SSF for calculation of the output resistance.

The output resistance can be calculated using the small-signal circuit shown in Figure 61, resulting in \[\begin{equation} R_{out} = \frac{G_{ds1}}{G_{m1}\,G_{m2}+G_{m2}\,G_{ds1}+G_{ds1}\,G_{ds2}} \cong \frac{G_{ds1}}{G_{m1}\,G_{m2}} \quad \textsf{for $G_{ds1} \ll G_{m1}$ and $G_{ds2} \ll G_{m2}$}. \end{equation}\] The output resistance of the SSF is equal to that of the SVF divided by \(G_{m2}/G_{ds1}\).

7.5.2.2 Transfer function

If we neglect the parasitic capacitances, it can be shown that the voltage gain is given by \[\begin{equation} A_v(s) = \frac{A_{dc}}{s/\omega_p + 1}, \end{equation}\] with \[\begin{align} A_{dc} &= \frac{G_{m1}\,G_{m2}}{G_{m1}\,G_{m2}+G_{m2}\,G_{ds1}+G_{ds1}\,G_{ds2}} \cong 1,\\ \omega_p &= \frac{G_{m1}\,G_{m2}+G_{m2}\,G_{ds1}+G_{ds1}\,G_{ds2}}{G_{ds1}\,C_L} \cong \frac{G_{m2}}{G_{ds1}}\,\frac{G_{m1}}{C_L}. \end{align}\] We see that the bandwidth of the SSF is extended by \(G_{m2}/G_{ds1}\) compared to that of the SVF. However, this turns out to be wrong because when taking the parasitic capacitances at the drain node of M₁ into account, results in a 2^nd-order low-pass transfer function which can have a quality factor larger than 1 and therefore show some peaking at the resonant frequency. This oviously leads to a ringing step response and a settling time that may be longer than that of the SVF. It may even lead to instability. This can be circumvented by adding a compensation capacitor that reduces the dominant pole of the open-loop transfer function and increases the non-dominant pole similarly to the pole splitting technique that is used for compensating two-stages OPAMPs. This comes at the cost of a reduced bandwidth which is then about equal to that of the SVF. However, the output resistance is significantly decreased.

If we assume that the bias current of M₁ and M₂ are equal to that of the SVF, the compensated SSF achieves about the same bandwidth than that of the SVF with a much lower resistance but at the cost of about twice its current consumption.

Quarto Notebook: Improved Voltage Followers

This Quarto notebook discusses the SSF in much more details and gives a design example with simulation.

7.5.3 The flipped voltage-follower (FVF)

Figure 62: The flipped voltage-follower (FVF) [15] [16] [17].

The main drawback of the SSF is the current consumption which is about twice that of the SVF to achieve the same bandwidth assuming that the circuit is compensated. We can actually reduce the current consumption by flipping the pMOS common-source (CS) stage into a nMOS CS which can fit below the voltage follower and share the same bias current. This results in the schematic of the flipped voltage follower (FVF) shown in Figure 62 [15] [16] [17]. It is called flipped because the pMOS CS of the SSF has been flipped into an nMOS CS (some say that the origin of flipped comes from flipping the current source of the SVF and moving it to the top [17]).

Similarly to the SSF, the FVF also features a feedback loop to reduce its output resistance. The feedback loop operates as follows: if the output voltage increases keeping a constant input voltage, the drain current of M₁ decreases and the drain voltage of M₁ and gate voltage of M₂ increase. Since the gate voltage of M₂ increases, its drain voltage now decreases bringing the output voltage back to its quiescent value. In other words, the FVF tries to keep the output voltage constant resulting in an output resistance that is significantly reduced compared to the SVF. We will analyze this in more details below. But before we proceed with the small-signal analysis, we need to have some large-signal considerations.

7.5.3.1 Large-signal considerations

The fact that the \(V_{GS}\) voltage of M₂ is equal to the sum of the \(V_{DS}\) voltages of M₁ and M₂ is seriously limiting the input voltage compliance. The lower limit of the input voltage corresponds to a zero output voltage and is therefore given by \(V_{GS1}\). If we assume that M₁ is biased in moderate inversion then \(V_{GS1} \cong V_{T0n}\) so the \(V_{in,min} \cong V_{T0}\). This lower limit is similar to that of the SFV.

The maximum input voltage is set by transistor M₁ getting into the linear region with \(V_{DS}\) close to zero and hence \(V_{in,max} \cong V_{GS1} + V_{GS2}\). If M₁ and M₂ are biased in weak or moderate inversion, \(V_{in,max} \cong 2\,V_{T0}\).

The input voltage swing is therefore \(\Delta V_{in} = V_{in,max} - V_{in,min} \cong V_{T0n}\) which is about one threshold voltage. For the 180 nm technology with \(V_{T0n} =\) 0.455, we get \(V_{in,max} =\) 0.910 \(V\), \(V_{in,min} =\) 0.455 \(V\). This leads to a very limited input voltage swing \(\Delta V_{in} =\) 0.455 \(V\).

7.5.3.2 Small-signal analysis

The small-signal schematic of the FVF is actually identical to that of the SSF. This means that the feedback loop also introduces some resonance resulting in a peaking at the resonance frequency and a ringing step response. The FVF can also be compensated to ensure enough phase margin in the open-loop transfer function and hence an acceptable step response. If the compensation capacitance is chosen equal to the load capacitance and both are assumed much larger than the parasitic capacitances, the bandwidth of the FVF for the same bias current is about equal to that of the SVF. On the other hand the output resistance is much lower thanks to the feedback loop. Therefore, the FVF is interesting for achieving a low output resistance without spending more current than the SVF thanks to the current sharing property of the FVF.

Quarto Notebook: Improved Voltage Followers

This Quarto notebook discusses the FVF in much more details and gives a design example with simulation.

7.6 Current mirrors

7.6.1 Principle

Many analog circuits make use of current sources to properly bias transistors with the right current to achieve the given specifications. The gates of these current sources are usually connected to a diode-connected reference transistor resulting in the current mirror shown in Figure 63. Current mirrors are used for bias purpose but can also be used to duplicate a current signal like for example in the simple OTA (or 5T OTA).

Figure 63: Principle of a current mirror

The current delivered by the current source M_k is either equal or proportional to the reference current \(I_0\) input to the diode-connected transistor M₀. If we can assume that the output conductances can be neglected and all transistors are in saturation, the various current ratioes that can be implemented are given by \[\begin{equation} \frac{I_k}{I_0} = \frac{I_{speck}}{I_{spec0}} = \frac{\beta_k}{\beta_0} = \begin{cases} 1 & \textsf{unit value},\\ \frac{m}{n} & \textsf{rational value},\\ \frac{W_k}{W_0} & \textsf{any value}. \end{cases} \end{equation}\] The current ratio \(I_k/I_0\) is ideally equal to 1 if transistor M_k is made identical to M₀. It can be a rational number if M_k and M₀ are made with \(m\), respectively \(n\), unit transistors in parallel. If needed, we can also make the current ratio \(I_k/I_0\) equal any value \(K\) by choosing \(W_k/W_0=K\) and \(L_k=L_0\).

Figure 64: Current mirror for implementing high current gains.

For implementing high current gains, we can use a combination of series/parallel transistors all in the same substrate (or well) as shown in Figure 64. For example, putting 4 transistors in series and in parallel as in Figure 64 results in \(I_2/I_1 = 16\). This technique is however less precise than parallel transistors only because of channel length modulation.

7.6.2 Small-signal analysis

(a) Schematic.

(b) Small-signal schmatic.

Figure 65: Basic current mirror.

Figure 65 (a) shows a basic current mirror with a current gain equal to \(B\). The schematic also shows the total capacitance at the gate node coming from the parasitic capacitances of M₁ and M₂. The corresponding small-signal schematic is shown in Figure 65 (b). It is easy to show that the small-signal current gain is given by \[\begin{equation} A_i(s) \triangleq \frac{\Delta I_2}{\Delta I_1} = \frac{B}{1+s/\omega_c}, \end{equation}\] with \[\begin{align} B &= \frac{G_{m2}}{G_{m1}},\\ \omega_c &= \frac{G_{m1}}{C}. \end{align}\]

If we assume that the two transistors M₁ and M₂ are identical, then the DC current gain \(B=1\). If additionally we assume that they are biased in SI then \(G_{m1}=G_{m2}=G_m \propto W \cdot V_{DSsat}\). On the other hand the parasitic capacitance \(C\) at the common gate is also proportional to the transistor width \(C \propto W\). Therefore the cut-off frequency is independent of \(W\) but proportional to \(V_{DSsat}\). Choosing a high \(V_{DSsat}\) allows to push the pole introduced by the mirror to high frequency.

Note

We have to distinguish current mirrors with DC currents that are used for biasing purpose only and current mirrors that include a current signal on top of a DC bias current (they are sometimes called “active current mirrors”). The dynamic behavior is obviously less important for bias current mirrors than for “active current mirrors”. For example, in amplifers like OTAs, the pole due to the parasitic capacitance at the common gate node usually needs to be set at a frequency higher than the gain-bandwidth product in order to secure enough phase margin. We will come back to this when design such OTAs.

On the other hand, for current mirrors that are used for bias purpose only, capacitance \(C\) can be made large by eventually adding a functional capacitance in order to filter out the noise coming from the bias circuit.

7.6.3 Noise analysis

Figure 66: Current-mirror small-signal schematic used for noise calculation.

The small-signal schematic of the current mirror of Figure 65 (a) that can be used for the noise calculation is shown in Figure 66, where \(I_{n1}\) and \(I_{n2}\) are the noise current sources of M₁ and M₂ including both thermal and flicker noise, \(I_{nin}\) is the eventual noise current imposed at the input and coming from previous stages. \(I_{nout}\) is the output noise current which is given by \[\begin{equation} I_{nout} = B\,(I_{nin}-I_{n1}) + I_{n2}. \end{equation}\] The PSD of the output noise current fluctuations assuming that all noise sources are uncorrelated is then given by \[\begin{equation}\label{eqn:7:cm:sinout} S_{I_{nout}} = B^2\,(S_{I_{nin}} + S_{I_{n1}}) + S_{I_{n2}}, \end{equation}\] where \[\begin{equation} S_{I_{ni}} = 4\,k_B\,T\,G_{ni} \quad \textsf{for $i=1,2$}. \end{equation}\] with \(G_{ni}\) given by \(\eqref{eqn:7:gni}\). Equation \(\eqref{eqn:7:cm:sinout}\) shows that the noise already present at the input and the noise coming from M₁ are multiplied by the square of the current gain \(B^2\). This is not a problem if the current mirror is an active current mirror carrying a signal current. Indeed, the current signal is therefore also amplified by the same gain and there is no signal-to-noise degradation. It is actually good to reduce the noise coming from the next stages, because when this noise is referred to the current mirror input, the noise is divided by \(B^2\). It might be a problem when introducing this current gain in a bias current mirror with the goal of reducing the DC input bias current which is wasted anyway. The noise of the input bias current is then multiplied by \(B^2\). So saving current at the input comes at the cost of more noise at the output.

We can rewrite the output noise current PSD as \[\begin{equation} \begin{split} S_{I_{nout}} &= B^2\,S_{I_{nin}} + 4\,k_B\,T\,\gamma_{n2}\,G_{m2}\left(1+\frac{G_{m2}}{G_{m1}}\,\frac{\gamma_{n1}}{\gamma_{n2}}\right)\\ &+ 4\,k_B\,T\,G_{m2}^2\,\frac{\rho_n}{f}\,\left(\frac{1}{W_1\,L_1}+\frac{1}{W_2\,L_2}\right), \end{split} \end{equation}\] If we assume that M₁ and M₂ are biased in SI we have \[\begin{align} G_{m1} &= \frac{2\,I_{in}}{n\,V_{DSsat}},\\ G_{m2} &= B\,G_{m1},\\ \gamma_{n1} &= \gamma_{n2} = \frac{2}{3}\,n. \end{align}\] where \(I_{in}\) is the DC input current. Replacing results in \[\begin{equation}\label{eqn:cm:SInout} \begin{split} S_{I_{nout}} &= B^2\,S_{I_{nin}} + \frac{16}{3}\,k_B\,T\,\frac{B\,I_{in}}{n\,V_{DSsat}}\,(1+B)\\ &+ 4\,k_B\,T\,\left(\frac{B\,I_{in}}{n\,V_{DSsat}}\right)^2\,\frac{\rho_n}{f}\,\left(\frac{1}{W_1\,L_1}+\frac{1}{W_2\,L_2}\right) \end{split} \end{equation}\] The output noise PSD can therefore be minimized by choosing \(V_{DSsat}\) as high as the voltage headroom allows for (or equivalently increasing the inversion factor since in SI \(V_{DSsat}=2\,U_T\,\sqrt{IC}\)).

Tip

If the current mirror is used for bias purpose only (no signal), we can add a capacitance at the gate node to filter out the noise coming from the input and from M₁. However the noise coming from M₂ will remain (both thermal and flicker noise).

7.6.4 Current mismatch

In the above large and small-signal analysis, we have neglected the effect of nonzero output conductance, considering transistor M₂ in Figure 65 (a) as an ideal current source. However, the output conductance of M₂ has an impact on the matching between the output current \(I_2\) compared to the input current \(I_1\). Despite M₁ and M₂ have the same gate voltage, their drain current may differ because of the output conductance of M₂, even if the transistors M₁ and M₂ are exactly identical. Accounting for the output conductance of M₂, the output current \(I_2\) is only exactly equal to \(I_1\) if the drain-to-source voltage of M₂ is equal to that of M₁ i.e. \(V_{DS2} = V_{DS1} = V_{GS1}\). In order to save some voltage headroom, the \(V_{DS2}\) voltage will not be set to be equal to \(V_{GS1}\) but lower. This results in an output current \(I_2\) that is lower than the input current \(I_1\). The quiescent \(V_{DS}\) voltage of M₂ is actually set by some other parts of the circuit. This effect is illustrated in Figure 67, where the input current \(I_1=4\,\mu A\) and the output current \(I_2\) is plotted versus the output voltage equal to \(V_{DS2}\). We clearly see that \(I_2\) is equal to \(I_1\) only when \(V_{DS2}=V_{GS1}=0.48\,V\). As we will see later, this structural mismatch may introduce some systematic offset voltage in differential OTAs.

Figure 67: Current mismatch due to different \(V_{DS}\) voltages

On top of this structural current mismatch, there is also a randomn mismatch. Assuming a current gain \(B=1\), the variance of the relative current difference due to this randomn mismatch is given by \[\begin{equation} \sigma_{\frac{\Delta I_D}{I_D}}^2 = \sigma_{\frac{\Delta \beta}{\beta}}^2 + \left(\frac{G_m}{I_D}\right)^2\,\sigma_{\Delta V_{T0}}^2\\ = \frac{1}{W\,L}\,\left[A_{\beta}^2 + \left(\frac{G_m}{I_D}\right)^2\,A_{\Delta V_{T0}}^2\right]. \end{equation}\] The current mismatch variance is bias dependent because of the \(G_m/I_D\) ratio which is given by \[\begin{equation} \frac{G_m}{I_D} = \begin{cases} \frac{2}{n\,V_{DSsat}} & \textsf{in SI},\\ \frac{1}{n\,U_T} & \textsf{in WI}. \end{cases} \end{equation}\] The current mismatch variance can be minimized by minimizing the \(G_m/I_D\) ratio and hence maximizing the saturation voltage \(V_{DSsat}\), which means that for better precision, the current mirror should be biased as much in strong inversion as the voltage headroom allows for.

Important

We have seen that bandwidth, output noise PSD and current mismatch are all optimized (maximized for bandwidth, minimized for noise PSD and mismatch) in strong inversion by maximizing the saturation voltage \(V_{DSsat}\).

7.6.5 Design procedure

A possible design flow for sizing a current mirror is given below.

1. Select maximum \(V_{DSsat}\) or \(IC\) compatible with requirements on:

• White noise PSD (avoid \(B>1\) for minimum noise),
• Speed,
• Relative contribution of \(V_T\)-mismatch to overall current mismatch.

2. Knowing the current \(I\), calculate the \(W/L\) ratio from \[\begin{equation*} \frac{W}{L} = \frac{I}{I_{spec\Box}\,IC} = \frac{I}{I_{spec\Box}\,\left(\frac{V_{DSsat}}{2\,U_T}\right)^2} = \frac{2\,I}{n\,\mu\,C_{ox}\,V_{DSsat}^2}. \end{equation*}\]

3. Use the second degree of freedom by selecting one of the following

• \(L=L_{min}\) for maxiumum speed,
• \(L\) large enough for large modulation voltage \(V_M\) (small output conductance),
• \(W\,L\) large enough for ensuring the required precision and/or limiting the \(1/f\) noise,
• \(L\) or \(W\) minimum for minimum area.

Note that some specs may not be compatible when imposing \(I\) and \(V_{DSsat}\) at the same time.

7.6.6 Improved current mirrors

7.6.6.1 Cascode current mirrors

(a) Cascode current mirror.

(b) Self-biased cascode current mirror.

Figure 68: Cascode current mirrors.

We have seen above that the output conductance of the output transistor can introduce some current mismatch in a current mirror. As shown in Figure 68 (a), we can reduce the output conductance and hence mitigate this effect by adding a cascode transistor M₂ to the current source M_1b. This circuit requires an additional bias voltage \(V_b\) that needs to be large enough for biasing M_1b in saturation. If we assume M_1b is biased in saturation, the output conductance is given by \[\begin{equation} G_{out} = \frac{G_{ds1b}}{G_{ms2}/G_{ds2}}. \end{equation}\] We could stack additional cascode transistors to further reduce the output conductance. However, in bulk technologies, we will be limited by the conductance of the reverse biased p-n junction at the drain of the top cascode transistor. Additionally this would require enough voltage headroom which is against the trend imposed by voltage scaling.

The bias voltage \(V_b\) can actually be generated without any additonal bias current string, just by connecting M_2b to an additional diode-connected transistor M_2a as shown in Figure 68 (b). Although this solution saves an another bias current string, it wastes a lot of voltage headroom. Indeed, with this circuit, by symmetry, the drain voltage of M_1b will be equal to the gate voltage \(V_{G1}\). This gate voltage is much larger than the drain voltage \(V_{D1b}\) required to bias M_1b in saturation \[\begin{equation} V_{D1b} = V_{G1} \gg V_{DSsat1b} = V_{P1} \cong (V_{G1}-V_{T0})/n_1. \end{equation}\] We basically loose a threshold voltage across the \(V_{DS}\) voltage of M_1b. We will see below how to circumvent this drawback.

Figure 69: Current mirror including regulated cascode transistors [3].

The output conductance can be reduced even further by using regulated cascodes in the current mirror as shown in Figure 69 [3]. In this case the \(V_{DS}\) voltage of M_1a-M_1b is not as low as \(V_{DSsat1}\) because it is set by the \(V_{GS}\) voltage of M_2a-M_2b which is close to \(V_{T0n}\) if they are biased in weak or moderate inversion.

7.6.6.2 Low-voltage cascode currents mirrors

Figure 70: Low-voltage cascode current mirror [18].

The output voltage compliance can be improved by using the low-voltage cascode current mirror shown in Figure 71 [18]. The bias voltage \(V_b\) should be set such that M_1a and M_1b are biased at the edge of saturation in order to increase the voltage swing at the output. The minimum output voltage is then equal to \(V_{DSsat1}+V_{DSsat2}\cong2\,V_{DSsat}\). This circuit however requires an additional bias circuit to generate the bias voltage \(V_b\) which can be implemented by using one of the scheme presented in Section 7.4.6.

7.6.6.3 Low input voltage compliance current mirrors

(a) Without cascode

(b) With cascode.

Figure 71: Low input voltage compliance current mirrors [19].

In some circuits we need to make sure that the current mirror still works with a low input voltage. The compliance to low input voltages can be improved compared to the normal current mirror by using the current mirror shown Figure 71 (a) [19]. Since M_1a and M_1b share the same gate node and hence the same gate voltage, they have the same drain current \(I_{1a}=I_{1b}\). This voltage is generated by M_1a and M₂ in series like in a normal current mirror. However, the input current is now injected at the drain of M_1a instead of the drain of M₂, saving some input voltage. Of course, while M₂ is biased in saturation, M_1a is operating in the linear region allowing for a low input voltage \(V_{in}\). Now, currents \(I_{1a}\) and \(I_{1b}\) include the input current \(I_{in}\) on top of a bias current \(I_b\). To recover the input current at the output, we need to add another bias current source at the output so that \(I_{out}=I_{1b}-I_b=I_{1a}-I_b=I_{in}\).

The output conductance of the current mirror Figure 71 (a) can be reduced by adding a cascode transistor as shown in Figure 71 (b) [19]. The gate voltage of M₃ is set by the negative feedback loop including M_1b, M_2b and M_2a. The output conductance can be obtained from a small-signal analysis assuming that M_1a-M_1b and M_2a-M_2b are perfectly matched and that the DC input and output currents are equal. In this case \(G_{m1a}=G_{m1b}=G_{m1}\), \(G_{md1a}=G_{md1b}=G_{md1}\), \(G_{m2a}=G_{m2b}=G_{m2}\), \(G_{ms2a}=G_{ms2b}=G_{ms2}\) and \(G_{ds2a}=G_{ds2b}=G_{ds2}\). Assuming in addition that \(G_{ds1} \ll G_{md1} < G_{m1}\) and \(G_{ds2} \ll G_{m2} < G_{ms2}\), the output conductance is approximately given by \[\begin{equation} G_{out} \triangleq \frac{\Delta I_{out}}{\Delta V_{out}} \cong G_{md1}\,\frac{G_{ds2}}{G_{ms2}}\,\frac{G_{ds3}}{G_{m3}}, \end{equation}\] which corresponds to the output conductance of a regulated cascode stage but with \(G_{ds1}\) replaced by \(G_{md1}\) which has been assumed much larger than \(G_{ds1}\).

Quarto Notebook: Improved Current Mirrors

This Quarto notebook discusses the improved current mirrors presented above in much more details with examples and simulations.

7.7 Differential pair

Figure 72: Differential pair schematic.

The differential pair is shown in Figure 72. It is made of two identical transistors M₁ and M₂ sharing the same source node. The differential pair is biased from the bottom by a current source which for the moment we will consider as ideal. Because the differential pair has two input voltages \(V_{i1}\) and \(V_{i2}\) and two output currents \(I_1\) and \(I_2\), we can define different gains (actually different transconductances). We can define the differential input voltage \(V_{id}\) and common-mode input voltage \(V_{ic}\) as \[\begin{align} V_{id} &= V_{i1}-V_{i2},\\ V_{ic} &= \frac{V_{i1}+V_{i2}}{2}. \end{align}\] Similarly, we also can define the differential output current \(I_{od}\) and common-mode output current \(I_{oc}\) as \[\begin{align} I_{od} &= I_1-I_2,\\ I_{oc} &= \frac{I_1+I_2}{2}. \end{align}\] The sum of the transistor currents \(I_1+I_2\) is actually equal to the bias current set by the bottom current \[\begin{equation} I_1 + I_ 2 = 2\,I_b. \end{equation}\] Therefore the output common-mode current is independent of the input differential and common-mode voltages and simply equal to the bias current \(I_b\) \[\begin{equation} I_{oc} =I_b. \end{equation}\]

The differential pair is an essential building block particularly for differential amplifiers. Any differential amplifier uses a differential pair or a modified version of it as input stage. The main reason is that the differential amplifier generates an output voltage that is proportional to the differential input voltage independently of its common-mode value. This is one of the main feature of the differential pair: it rejects the common mode input voltage \(V_{ic}\) and only handles the differential voltage \(V_{id}\).

We will now perform a large-signal analysis of the differential pair first assuming both transistors are biased in weak inversion and saturation, and then in strong inversion and saturation. We then will use the EKV model to derive an expression of the large-signal behavior that is valid in any modes of operation (saturation).

7.7.1 Large-signal analysis

7.7.1.1 Both transistors in weak inversion

In the following analysis, we will assume that M₁ and M₂ are perfectly matched, meaning that \[\begin{align} V_{T01} &= V_{T02} = V_{T0},\\ I_{D01} &= I_{D02} = I_{D0},\\ n_1 &= n_2 =n. \end{align}\] In the case both transistors are biased in weak inversion and saturation and since M₁ and M₂ are in the common substrate (i.e. have their bulk terminals connected to the ground), the drain currents are then given by \[\begin{align} I_1 &= I_{D0} \cdot e^{\frac{V_{i1}-n\,V_S}{n U_T}},\\ I_2 &= I_{D0} \cdot e^{\frac{V_{i2}-n\,V_S}{n U_T}}. \end{align}\] The differential output current is then given by \[\begin{equation}\label{eqn:iod1} I_{od} \triangleq I_1-I_2 = I_{D0} \cdot e^{-\frac{V_S}{U_T}} \cdot \left[e^{\frac{V_{i1}}{n U_T}}-e^{\frac{V_{i2}}{n U_T}}\right]. \end{equation}\] Now, the sum of \(I_1\) and \(I_2\) is set by the bottom current source \[\begin{equation} I_1+I_2 = 2 I_b, \end{equation}\] leading to \[\begin{equation} 2 I_b = I_{D0} \cdot e^{-\frac{V_S}{U_T}} \cdot \left[e^{\frac{V_{i1}}{n U_T}}+e^{\frac{V_{i2}}{n U_T}}\right] \end{equation}\] from which we get \[\begin{equation}\label{eqn:exp_vs} I_{D0} \cdot e^{-\frac{V_S}{U_T}} = \frac{2 I_b}{e^{\frac{V_{i1}}{n U_T}}+e^{\frac{V_{i2}}{n U_T}}} \end{equation}\] Replacing \(\eqref{eqn:exp_vs}\) in \(\eqref{eqn:iod1}\) results in \[\begin{equation}\label{eqn:iod2} I_{od} = 2 I_b \cdot \frac{e^{\frac{V_{i1}}{n U_T}}-e^{\frac{V_{i2}}{n U_T}}} {e^{\frac{V_{i1}}{n U_T}}+e^{\frac{V_{i2}}{n U_T}}}. \end{equation}\] The input voltages can be written in terms of the differential and common mode voltages according to \[\begin{align} V_{i1} &= V_{ic} + \frac{V_{id}}{2},\\ V_{i2} &= V_{ic} - \frac{V_{id}}{2}. \end{align}\] Replacing in \(\eqref{eqn:iod2}\) results in \[\begin{equation}\label{eqn:iod3} I_{od} = 2 I_b \cdot \frac{e^{\frac{V_{id}}{2 n U_T}}-e^{-\frac{V_{id}}{2 n U_T}}} {e^{\frac{V_{id}}{2 n U_T}}+e^{-\frac{V_{id}}{2 n U_T}}} = 2 I_b \cdot \tanh\left(\frac{V_{id}}{2 n U_T}\right). \end{equation}\] The differential output current \(I_{od}\) normalized to \(2 I_b\) can then be written as \[\begin{equation} i_{od} \triangleq \frac{I_{od}}{2 I_b} = \tanh(v_{id}), \end{equation}\] where \(v_{id} \triangleq V_{id}/(2n U_T)\).

Figure 73: Differential current \(i_{od}\) and transconductance \(g_m\) versus differential input voltage \(v_{id}\) for both transistors M₁ and M₂ biased in weak inversion and saturation.

The normalized differential output current \(i_{od}\) is plotted versus the normalized differential input voltage \(v_{id}\) in Figure 73. We see that the large-signal nonlinear characteristic can be approximated by a piecewise linear characteristic where the middle part has the slope of the nonlinear characteristic at \(v_{id}=0\). The linear range can then be defined as the input voltage covered by the middle linear characteristic. In weak inversion the linear range is about \(4 n U_T\) which is about 135 mV at room temperature for \(n=1.3\). This is rather small.

7.7.1.2 Both transistors in strong inversion

We again will assume that the two transistors are perfectly matched, which means that \[\begin{align} V_{T01} &= V_{T02} = V_{T0},\\ \beta_1 &= \beta_2 = \beta,\\ n_1 &= n_2 =n. \end{align}\] In the case both transistors are biased in strong inversion and saturation and since M₁ and M₂ are in the common substrate (i.e. have their bulk terminals connected to the ground), the drain currents are given by \[\begin{align} I_1 &= \frac{\beta}{2 n} \cdot (V_{i1}-V_{T0}-n\,V_S)^2,\\ I_2 &= \frac{\beta}{2 n} \cdot (V_{i2}-V_{T0}-n\,V_S)^2, \end{align}\] where \(V_S\) is the voltage of the common source node. Solving the above equations together with \[\begin{align} I_{od} &= I_1-I_2,\\ I_1+I_2 &= 2 I_b,\\ V_{i1} &= V_{ic}+\frac{V_{id}}{2},\\ V_{i2} &= V_{ic}-\frac{V_{id}}{2},\\ V_{id} &= V_{i1}-V_{i2}, \end{align}\] leads to \[\begin{equation} I_{od} = V_{id} \cdot \sqrt{\frac{2 \beta I_b}{n}} \cdot \sqrt{1-\frac{\beta}{2 n I_b} \cdot \left(\frac{V_{id}}{2}\right)^2} \end{equation}\] valid for \[\begin{equation} |V_{id}| < 2 \sqrt{\frac{2 n I_b}{\beta}} = 2 (V_{ic}-V_{T0}-V_S). \end{equation}\] The differential output current \(I_{od}\) can be normalized to the maximum output current \(2 I_b\) \[\begin{equation} i_{od} \triangleq \frac{I_{od}}{2 I_b} = v_{id} \cdot \sqrt{1 - \left(\frac{v_{id}}{2}\right)^2}, \end{equation}\] valid for \[\begin{equation} |v_{id}| < \sqrt{2}, \end{equation}\] where \[\begin{equation} v_{id} \triangleq \frac{V_{id}}{\sqrt{2 n I_b/\beta}} = \frac{V_{id}}{V_G-V_{T0}- n\,V_S}. \end{equation}\]

Figure 74: Differential current \(i_{od}\) and transconductance \(g_m\) versus differential input voltage \(v_{id}\) for both transistors M₁ and M₂ biased in strong inversion and saturation.

The large-signal normalized differential output current \(i_{od}\) is plotted versus \(v_{id}\) in Figure 74. Similarly to what has been done in weak inversion we can approximate the nonlinear characteristic by a piecewise linear model as shown in Figure 74. The linear range is now proportionnal to the overdrive voltage according to \(2(V_G-V_{T0}-n\,V_S)\), which is much larger than what we get in weak inversion. We can therefore make the differential pair more linear by increasing the overdrive voltage. However, this comes at the cost of a reduced current efficiency \(G_m/I_b\). This point will be discussed in more details in Chapter 11 Continuous-time Filters (CTFs).

7.7.1.3 Both transistors in any modes of operation (saturation) [20]

In the previous sections, we have derived the large-signal differential voltage-to-current transfer characteristic in weak and in strong inversion. We now will show that we can actually derive the inverse differential transfer characteristic (i.e. differential input voltage in terms of the differential output current) in any modes of inversion. In order to do this, we first use the EKV charge-based model to express the gate voltages of M₁ and M₂ in terms of \(q_{s1}\) and \(q_{s2}\) according to \[\begin{align} \frac{V_{i1}-V_{T0}-n\,V_S}{n\,U_T} &= 2 q_{s1} + \ln(q_{s1}),\\ \frac{V_{i2}-V_{T0}-n\,V_S}{n\,U_T} &= 2 q_{s2} + \ln(q_{s2}). \end{align}\] If we want to be consistent with the analysis of the differential pair in weak inversion we need to use the same normalization. This means that the voltages need to be normalized to \(2 n\,U_T\), leading to \[\begin{align} v_{i1}-v_{t0n}-v_s &= q_{s1} + \tfrac{1}{2}\,\ln(q_{s1}),\label{eqn:vi1_vt0_vs}\\ v_{i2}-v_{t0n}-v_s &= q_{s2} + \tfrac{1}{2}\,\ln(q_{s2}),\label{eqn:vi2_vt0_vs} \end{align}\] where \[\begin{align} v_{i1} &\triangleq \frac{V_{i1}}{2 n U_T},\\ v_{i2} &\triangleq \frac{V_{i2}}{2 n U_T},\\ v_s &\triangleq \frac{V_S}{2 n U_T}. \end{align}\] The normalized differential input voltage \(v_{id}\) is then given by subtracting \(\eqref{eqn:vi2_vt0_vs}\) to \(\eqref{eqn:vi1_vt0_vs}\) resulting in \[\begin{equation}\label{eqn:vid_qs1_qs2} v_{id} \triangleq \frac{V_{id}}{2 n\,U_T} = v_{i1}-v_{i2} = q_{s1}-q_{s2}+\tfrac{1}{2}\,\ln\left(\frac{q_{s1}}{q_{s2}}\right) \end{equation}\]

We need to be careful with the normalization of the currents. In order to have the output differential current \(I_{od}=I_1-I_2\) normalized to the maximum output current \(2 I_b\), like it was done for the analysis in weak and strong inversion, we need to define the normalized currents \(i_1\), \(i_2\) and \(i_{od}\) as \[\begin{align} i_1 &\triangleq \frac{I_1}{2 I_b},\\ i_2 &\triangleq \frac{I_2}{2 I_b},\\ i_{od} &\triangleq \frac{I_{od}}{2 I_b} = \frac{I_1-I_2}{2 I_b} = i_1-i_2. \end{align}\] Assuming that M₁ and M₂ are biased in saturation, the normalized source charges \(q_{s1}\) and \(q_{s2}\) are related to the normalized drain currents \(i_{d1}\) and \(i_{d2}\) according to \[\begin{align} i_{d1} &\triangleq \frac{I_1}{I_{spec}} = q_{s1} \cdot (q_{s1}+1),\\ i_{d2} &\triangleq \frac{I_2}{I_{spec}} = q_{s2} \cdot (q_{s2}+1). \end{align}\] Notice that \(i_1\) and \(i_2\) are different than \(i_{d1}\) and \(i_{d2}\) since the former are normalized to \(2 I_b\), whereas the latter are normalized to \(I_{spec}\). They are related according to \[\begin{align} i_1 &= \frac{i_{d1}}{2 IC_q},\\ i_2 &= \frac{i_{d2}}{2 IC_q}, \end{align}\] where \[\begin{equation} IC_q \triangleq \frac{I_b}{I_{spec}} \end{equation}\] corresponds to the inversion coefficient of M₁ and M₂ at the quiescent operating point, i.e. for \(V_{id}=0\).

Solving the above set of equations for \(q_{s1}\) and \(q_{s2}\) results in \[\begin{align} q_{s1} &= \frac{\sqrt{4 IC_q\,(1+i_{od})+1}-1}{2},\label{eqn:qs1_iod}\\ q_{s2} &= \frac{\sqrt{4 IC_q\,(1-i_{od})+1}-1}{2}.\label{eqn:qs2_iod} \end{align}\] We can now sweep the normalized differential output current for a given \(IC_q\) and then calculate \(q_{s1}\) and \(q_{s2}\) according to \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\) and use them to calculate \(v_{id}\) according to \(\eqref{eqn:vid_qs1_qs2}\). The result is plotted in Figure 75 for different \(IC_q\).

Figure 75: Differential current \(i_{od}\) versus differential input voltage \(v_{id}\) valid in all regions of operation (assuming M₁ and M₂ in saturation).

We clearly see that increasing the inversion coefficient \(IC_q\) from weak inversion to strong inversion extends the linear range from \(4 n U_T\) to \(2(V_{ic}-V_{T0}-nV_S)\), where \(V_{ic} \triangleq (V_{i1}+V_{i2})/2\) is the input common-mode voltage. However this comes at the cost of a reduced transconductance efficiency \(G_{m0}/I_b\).

7.7.2 Small-signal analysis

7.7.2.1 Both transistors in weak inversion

The small-signal transconductance is defined by \[\begin{equation} G_m \triangleq \frac{d I_{od}}{d V_{id}} = G_{m0} \cdot \left[1 - \tanh^2\left(\frac{V_{id}}{2 n U_T}\right)\right] \end{equation}\] where \(G_{m0}\) is the transconductance for \(V_{id}=0\) \[\begin{equation} G_{m0} = \frac{I_b}{n U_T}. \end{equation}\] The maximum transconductance \(G_{m0}\) of the differential pair therefore corresponds to the transconductance of a single transistor for \(V_{id}=0\) (i.e. when \(I_1=I_2=I_b\)).

The small-signal transconductance normalized to \(G_{m0}\) is then given by \[\begin{equation} g_m \triangleq \frac{G_m}{G_{m0}} = 1-\tanh^2\left(v_{id}\right). \end{equation}\]

The small-signal transconductance in weak inversion normalized to \(G_{m0}\) is plotted versus \(v_{id}\) in Figure 74 (blue curve corresponding to the right y-axis).

7.7.2.2 Both transistors in strong inversion

The small-signal transconductance is defined as \[\begin{equation} G_m \triangleq \frac{d I_{od}}{d V_{id}}, \end{equation}\] which is given by \[\begin{equation} G_m = G_{m0} \cdot \frac{2-v_{id}^2}{\sqrt{4-v_{id}^2}}, \end{equation}\] where \[\begin{equation} G_{m0} = \sqrt{\frac{2 \beta I_b}{n}} \end{equation}\] is the transconductance for \(V_{id}=0\) which also corresponds to the transconductance of M₁ or M₂ for \(V_{id}=0\).

The normalized small-signal transconductance in strong inversion is plotted versus \(v_{id}\) in Figure 74 (blue curve corresponding to the right y-axis).

7.7.2.3 Both transistors in any modes of operation (saturation)

In the previous section we have derived an expression of \(V_{id}\) in terms of \(q_{s1}\) and \(q_{s2}\) which depend on \(I_{od}\). We can derive the transconductance by differentiating \(V_{id}\) wrt \(I_{od}\) \[\begin{equation} \frac{dV_{id}}{dI_{od}} = \frac{1}{G_m} \end{equation}\] or in normalized form \[\begin{equation} \frac{dv_{id}}{di_{od}} \cdot \frac{2 n\,U_T}{2 I_b} = \frac{1}{G_m}. \end{equation}\] The transconductance can then be written as \[\begin{equation} G_m \cdot \frac{n\,U_T}{I_b} = \left(\frac{dv_{id}}{di_{od}}\right)^{-1} = \frac{di_{od}}{dv_{id}} = g_m. \end{equation}\] so that \[\begin{equation} g_m \triangleq \frac{di_{od}}{dv_{id}} = \frac{G_m}{I_b/(n\,U_T)}. \end{equation}\] It can be shown that \[\begin{equation} g_m = \frac{4}{IC_q} \cdot \frac{q_{s1} \cdot q_{s2}}{q_{s1}+q_{s2}} \end{equation}\] with \(q_{s1}\) and \(q_{s2}\) given by \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\).

Now, we want to plot \(g_m\) normalized to its value at \(v_{id}=0\) \[\begin{equation} g_{m0} \triangleq g_m(v_{id}=0). \end{equation}\] For \(v_{id}=0\), we have \(i_{od}=0\) and from \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\), we get \[\begin{equation}\label{eqn:qs_ICq} q_s \triangleq \left.q_{s1}\right|_{v_{id}=0} = \left.q_{s2}\right|_{v_{id}=0} = \frac{\sqrt{4 IC_q+1}-1}{2}. \end{equation}\] \(g_{m0}\) can therefore be written as \[\begin{equation} g_{m0} = \frac{q_s}{IC_q} = \frac{\sqrt{4 IC_q+1}-1}{2 IC_q}. \end{equation}\] The transconductance normalized to the value it takes at \(v_{id}=0\) is therefore given by \[\begin{equation} \frac{G_m}{G_{m0}} = \frac{g_m}{g_{m0}} = \frac{2}{q_s} \cdot \frac{q_{s1} \cdot q_{s2}}{q_{s1}+q_{s2}} \end{equation}\] with \(q_s\), \(q_{s1}\) and \(q_{s2}\) given by \(\eqref{eqn:qs_ICq}\), \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\), respectively.

The normalized transconductance \(g_m\) is plotted versus the normalized differential input voltage \(v_{id}\) in Figure 76 for different values of the inversion coefficient \(IC_q\).

Figure 76: Transconductance normalized to its value at \(v_{id}=0\) versus differential input voltage \(v_{id}\) valid in all regions of operation (assuming M₁ and M₂ in saturation).

Figure 76 shows that increasing the quiescent inversion coefficient \(IC_q\) and moving to strong inversion extends the linear range making the differential pair more linear. This comes at the cost of decreasing the current efficincy \(G_m/I_b\).

7.7.3 Noise analysis

For the noise analysis, the small-signal input voltages are zero (\(\Delta V_{i1}=\Delta V_{i2}=V_{id}=0\)). The differential small-signal output noise current is then \[\begin{equation} \Delta I_{odn} = I_{n1} - I_{n2}. \end{equation}\] where \(I_{n1}\) and \(I_{n2}\) are the noise currents produced by M₁ and M₂. We can consider that these noise sources are uncorrelated so that the PSD of the output noise current fluctuations is given by \[\begin{equation} S_{\Delta I_{odn}} = S_{I_{n1}} + S_{I_{n2}} = 4\,k_B\,T\,G_{nout}, \end{equation}\] where \[\begin{equation} S_{I_{ni}} = 4\,k_B\,T\,G_{ni} \quad \textsf{for $i=1,2$}, \end{equation}\] and \[\begin{equation} G_{nout} = G_{n1} + G_{n2}, \end{equation}\] with \(G_{ni}\) given by \(\eqref{eqn:7:gni}\).

For \(V_{id}=0\), and assuming M₁ and M₂ are perfectly matched, M₁ and M₂ have the same bias current \(I_b\) and therefore the same transconductance \(G_m\) and same noise conductance \(G_n\) \[\begin{equation} G_n = \gamma_n\,G_m + G_m^2\,\frac{\rho_n}{W\,L\,f}. \end{equation}\] The output noise conductance is then simply twice the noise conductance of a single transistor \[\begin{equation} G_{nout} = 2\,G_n. \end{equation}\] We can refer the output noise to the input by dividing \(G_{nout}\) by the square of the equivalent transconductance which is actually equal to the transconductance of a single transistor \(G_m\). This results in the input-referred noise resistance \[\begin{equation} R_{nin} = \frac{G_{nout}}{G_m^2} = R_{nt} + R_{nf} \end{equation}\] where \(R_{nt}\) is the input-referred thermal noise resistance \[\begin{equation} R_{nt} = 2\,\frac{\gamma_n}{G_m} = \frac{\gamma_{neq}}{G_m}. \end{equation}\] \(\gamma_{neq}\) is the thermal noise excess factor of the differential pair which is simply equal to twice the thermal noise excess factor of a single transistor \[\begin{equation} \gamma_{neq} = 2\,\gamma_n. \end{equation}\] \(R_{nf}\) is the input-referred flicker noise resistance \[\begin{equation} R_{nf} = 2\,\frac{\rho_n}{W\,L\,f}. \end{equation}\]

We could have found the noise voltages at the gates of M₁ and M₂. Since they are connected in series they sum-up and again considering that they are uncorrelated we get the above result directly.

7.7.4 Effect of asymmetries

In the previous sections we have assumed that M₁ and M₂ were perfectly matched. Of course this is not the case. In quiescent state the gates of both transistors M₁ and M₂ are connected to the common-mode input voltage. Because of mismatch, the two output currents \(I_1\) and \(I_2\) are not equal. We can reuse the above noise analysis where the noise currents \(I_{n1}\) and \(I_{n2}\) are replaced by \[\begin{align} I_{n1} &= +\frac{\Delta I_D}{2},\\ I_{n2} &= -\frac{\Delta I_D}{2}. \end{align}\] The differential output current due to mismatch is then simply equal to \(I_{od} = \Delta I_D\). We have seen that the variance of this current mismatch is given by \[\begin{equation} \sigma_{\Delta I_D}^2 = I_b^2\,\sigma_{\frac{\Delta \beta}{\beta}}^2 + G_m^2\,\sigma_{\Delta V_{T0}}^2, \end{equation}\] where \[\begin{align} \sigma_{\frac{\Delta \beta}{\beta}}^2 &= \frac{A_{\beta}^2}{W\,L},\\ \sigma_{\Delta V_{T0}}^2 &= \frac{A_{\Delta V_{T0}}^2}{W\,L}. \end{align}\] We can refer this output current mismatch to the input by dividing its variance by \(G_m^2\) resulting in the input offset voltage having a variance given by \[\begin{equation} \sigma_{V_{os}}^2 = \frac{\sigma_{\Delta I_D}^2}{G_m^2} = \sigma_{\Delta V_{T0}}^2 + \left(\frac{I_b}{G_m}\right)^2\,\sigma_{\frac{\Delta \beta}{\beta}}^2 = \frac{1}{W\,L}\,\left[A_{\Delta V_{T0}}^2 + \left(\frac{I_b}{G_m}\right)^2\,A_{\beta}^2\right] \end{equation}\] In order to minimize the input-referred offset voltage variance, we need to minimize the \(I_b/G_m\) ratio which means biasing the differential pair in weak inversion. In this case the contribution due to the \(\beta\)-mismatch can be neglected and the standard deviation of the offset voltage reduces to \[\begin{equation} \sigma_{V_{os}} = \frac{A_{\Delta V_{T0}}}{\sqrt{W\,L}}. \end{equation}\]

7.8 Voltage and Current references

7.8.1 Pinch-off voltage extraction

Figure 77: \(V_P\) versus \(V_G\) extractor circuit [8].

The pinch-off voltage is not only a convenient concept established for the development of the EKV MOSFET model, but it can be measured or extracted and used to properly bias some circuits. Since the pinch-off voltage can be interpreted as the effect of the gate voltage referred to the channel, it should be possible to measure it for example at the source end of the device. Considering the expression of the saturation voltage versus inversion coefficient of a transistor biased in saturation, which is repeated below for conveniance, \[\begin{equation*} v_p-v_s = \ln\left(\sqrt{4\,IC+1}-1\right)+\sqrt{4\,IC+1}-1-\ln(2), \end{equation*}\] the source voltage becomes equal to the pinch-off voltage if the RHS of the above equation becomes zero. This happens for a particular value of the inversion coefficient equal to \(IC \cong\) 0.6. If we bias the transistor shown in Figure 77 with a bias current equal to 0.6\(\times I_{spec}\) and we sweep the gate voltage, the source voltage will be equal to the pinch-off voltage \(V_P\). Note that this circuit can be used to extract the threshold voltage corresponding to the intersection of the curve with the zero line.

Figure 78: Simulated \(V_P\)-\(V_G\) characteristic using circuit shown in Figure 77.

Figure 78 shows the \(V_S \cong V_P\) versus \(V_G\) characteristic simulated with EKV 2.6 for a wide and long channel nMOS transistor from a generic 180nm bulk CMOS technology. The value of the gate voltage at which the curve crosses the zero line is simply the threshold voltage \(V_{T0} \cong 0.454\,V\) which is very close to the parameter value \(V_{T0} = 0.455\,V\) used in the EKV 2.6 compact model used for simulation. We can also extract the parameters \(\Gamma_b\) and \(\Psi_0\) used in the theoretical expression \[\begin{equation*} V_P = V_G-V_{T0}-\Gamma_b\,\left[\sqrt{V_G-V_{T0}+\left(\frac{\Gamma_b}{2}+\sqrt{\Psi_0}\right)^2}-\left(\frac{\Gamma_b}{2}+\sqrt{\Psi_0}\right)\right]. \end{equation*}\] We see that their values are very close to the ones used for simulation in the EKV 2.6 compact model. The dashed line in Figure 78 corresponds to the approximation we have been using \[\begin{equation*} V_P \cong \frac{V_G-V_{T0}}{n} \end{equation*}\] where the value of the slope factor \(n\) is taken at \(V_P=0\) \[\begin{equation*} n = n_0 = 1 + \frac{\Gamma_b}{2\,\sqrt{\Psi_0}} \cong 1.3. \end{equation*}\]

(a) Fraction of \(V_P\).

(b) \(V_R \cong V_P/2\).

Figure 79: Pinch-off voltage extractors [8].

A fraction of the pinch-off voltage can be extracted using the circuit presented in Figure 80 (a). In this case the bias current is chosen such that M₁ and M₂ are biased in strong inversion. Since the gate of M₂ is connected to its drain terminal, M₂ operates in saturation, while M₁ is assumed to operate in the linear region. Since both transistors M₁ and M₂ share the same gate, they have the same pinch-off voltage \(V_P\) and the same slope factor \(n\). Equating their drain currents and solving for \(V_R\) results in [8] \[\begin{equation} V_R = \left(1 - \frac{1}{\sqrt{1+\beta_2/\beta_1}}\right) \cdot V_P. \end{equation}\] It is convenient to implement the \(\beta\) ratio by using series association of several identical unit transistors. For example, M₁ and M₂ can be implemented by four stacked unit transistors in the same well as shown in Figure 79 (b). M₁ and M₂ will therefore have the same width (the width of one unit transistor) and if \(V_R\) is tapped at the source of the upper transistor, then \(\beta_2 = 3\,\beta_1\) and thus \(V_R = V_P/2\).

7.8.2 PTAT voltage sources

The circuit shown in Figure 80 (a) can also be used in weak inversion to realize a simple voltage source that provides a reference voltage that is proportionnal to absolute temperature or PTAT voltage reference. M₁ is again assumed to be in the linear region, whereas M₂ is in saturation. Equating the drain currents results in \[\begin{equation} V_R = U_T\,\ln\left(1 + \frac{\beta_2}{\beta_1}\right) \end{equation}\]

(a) Single PTAT voltage.

(b) Stacked PTAT voltages.

Figure 80: PTAT voltage references in weak inversion [8].

Because of the logarithmic dependence of \(V_R\) on the \(\beta_2/\beta_1\) ratio, this circuit can only realize PTAT voltages that are typically smaller than \(3\,U_T\) (i.e. \(\beta_2/\beta_1 \cong 19\)). Larger PTAT voltages can be achieved by simply stacking the same two transistor scheme and trading \(\beta\) ratios against current ratios as shown in Figure 80 (b). The original ratio is then multiplied by a factor equal to the ratio of the currents flowing in the lower and respectively in the upper transistor [8] \[\begin{align} V_{R1} &= U_T\,\ln\left(1+\frac{\beta_2}{\beta_1} \cdot \frac{I_{D1}}{I_{D2}}\right),\\ V_{R3} &= U_T\,\ln\left(1+\frac{\beta_4}{\beta_3} \cdot \frac{I_{D3}}{I_{D4}}\right). \end{align}\] If \(I_{D2} = I_{D4} = I_b\) and \(\beta_2/\beta_1 = \beta_4/\beta_3 = \alpha\), the stacked voltage \(V_{Rtot}\) is then equal to [8] \[\begin{equation} V_{Rtot} = U_T\,\ln[(1+2\,\alpha)(1+\alpha)]. \end{equation}\]

The principle of Figure 80 (b) can be extended to \(N\) stacked identical PTAT voltage sources driven by equal bias currents. This leads to \[\begin{equation}\label{eqn:7:vrtot} \frac{V_{Rtot}}{U_T} = N \cdot \ln(\alpha) + \ln[\Gamma(N+1+1/\alpha)] - \ln[\Gamma(1+1/\alpha)], \end{equation}\] where \(\Gamma(x)\) is the Gamma function. Equation \(\eqref{eqn:7:vrtot}\) is plotted versus the number of stacked PTAT voltage sources \(N\) for different values of the \(\beta\)-ratio \(\alpha\).

Figure 81: Voltage of \(N\)-stacked PTAT voltage sources [8].

From Figure 81 we see that with \(\alpha =\) 9 and \(N =\) 6, we get \(V_{Rtot} \cong\) 20 \(U_T \cong\) 0.518 \(V\) at room temperature. We might think that stacking the PTAT sources, we are quickly limited by the supply voltage. If we assume \(N =\) 6 stages, the minimum supply voltage for building a PTAT voltage \(V_{Rtot} \cong\) 0.518 \(V\) with \(V_{GS} \cong V_{T0} =\) 0.455 \(V\) and \(V_{DSsat} =\) 200 \(mV\) is \(V_{DD,min} =\) 1.069 \(V\). So this schematic can also be used at low voltage. Of course stacking \(N\) PTAT sources comes at the cost of a current consumption that is \(N\)-times \(I_b\).

7.8.3 The Vittoz voltage and current reference

Figure 82: Supply-referenced current generator.

Probably the simplest way to generate a reference current is to use the supply voltage combined with a resistance \(R\) as shown in Figure 82. The reference current is then given by \[\begin{equation} I_{out} = I_{ref} = \frac{V_{DD} - V_{G1}}{R} \end{equation}\] with \[\begin{equation} V_{G1} \cong V_{T0} +n\,V_{P1} = V_{T0} +n\,U_T\,\left[\ln\left(\sqrt{4\,IC_1+1}-1\right)+\sqrt{4\,IC_1+1}-1-\ln(2)\right] \end{equation}\] The current generator of Figure 82 has many drawbacks: it is strongly dependent on the supply voltage, on the process parameters such as the threshold voltage and on the resistance variations. Additionally, the current generator of Figure 82 is not well suited for low current generation since it may require very large resistance. Ideally we would like to have a current reference that is independent of the supply voltage and as little dependent on the process parameters and temperature as possible.

(a) With M₃ in common substrate.

(b) With M₃ in a separate well.

Figure 83: The Vittoz voltage and current reference [21].

The simplest supply-independent or self-biased current and voltage reference is the Vittoz current reference shown in Figure 83. The circuit is made of nMOS transistors M₁ and M₃ where M₃ is made \(K\)-times larger than M₁ (i.e. \(\beta_3 = K \cdot \beta_1\)). The pMOS current mirror M₂-M₄ which are made identical to provide a unity current gain, is imposing that the currents flowing in M₁ and M₂ are equal. Because M₃ is \(K\)-times larger than M₁, it requires less \(V_{GS}\) voltage than M₁ to drive the same current. Therefore, a voltage \(V_R\) builds-up across resistor \(R\). The value of this reference voltage \(V_R\) depends whether M₁-M₃ are biased in weak or strong inversion. We will examine each case separately below. Transistor M₃ can be either in the common substrate as shown in Figure 83 (a), or in a separate well as shown in Figure 83 (b).

(a) Core of the Vittoz reference [22] [23] [24].

(b) Output versus input current [22] [23] [24].

Figure 84: The core of the Vittoz current reference and its operation [21] [22] [23] [24].

To better understand its operation let’s have a closer look at the core circuit namely transistors M₁-M₃ which are redrawn in Figure 84 (a). If resistance \(R\) is set to zero, M₁-M₃ operate like a current mirror and since M₃ is made \(K\)-times larger than M₁, the output current is equal to \(K\,I_{in}\) as shown in Figure 84 (b). As we sweep the input current \(I_{in}\) starting from zero, the output current starts to increase with a slope \(K\). But as the output current increases, the voltage drop across the degeneration resistance \(R\) also increases reducing the \(V_{GS}\) voltage of M₃ and its drain current \(I_{out}\). This bends the input-output current characteristic as shown in Figure 84 (b). Now in the Vittoz current reference of Figure 83 (a), the pMOS current mirror M₂-M₄, which are identical, forces the output current \(I_{out}\) to be equal to the input current \(I_{in}\) as shown in Figure 84 (b) by the dashed line tagged M₂-M₄. As the current increases, it reaches the operating point P corresponding to the intersection of the M₁-M₃ and M₂-M₄ characteristics.

We now will derive the expressions of the reference voltage \(V_R\) and current \(I_b\) first in the case M₁-M₃ are biased in weak inversion and then in strong inversion.

7.8.3.1 Weak inversion

If we first analyze the circuit of Figure 83 (a), assuming that M₁-M₃ are biased in weak inversion, it is easy to show that this reference voltage is given by \[\begin{equation}\label{eqn:7:vr_wi} V_R = R\,I_b = U_T \cdot \ln(K). \end{equation}\] The reference voltage \(V_R\) is proportionnal to \(U_T = k_B\,T/q\) and therefore proportionnal to absolute temperature \(T\). The Vittoz reference of Figure 83 (a) is therefore a PTAT reference voltage.

In case M₃ is in a separate well, as shown in Figure 83 (b), the reference voltage is given by \[\begin{equation} V_R = R\,I_b = n\,U_T \cdot \ln(K), \end{equation}\] where \(n\) is the slope factor of M₁ and M₃.

The circuit can also generate a reference current which is set by the reference voltage \(V_R\) and the resistance \(R\) according to \[\begin{equation} I_b = \frac{V_R}{R} = \frac{U_T}{R} \cdot \ln(K). \end{equation}\] Of course, this reference current is only PTAT if the resistance \(R\) is temperature independent. If this bias current is used to bias a nMOS transistor biased in weak inversion then its transconductance is given by \[\begin{equation} G_m = \frac{I_b}{n\,U_T} = \frac{\ln(K)}{n\,R}. \end{equation}\] The transconductance is inversely proportionnal to the resistance. We can therefore set the transconductance of a nMOS transistor to be inversely proportionnal to a resistance and if the latter is temperature independent the transconductance is also temperature independent.

7.8.3.2 Strong inversion

The Vittoz current reference also works if transistors M₁-M₃ are biased in strong inversion. In this case the reference voltage is given by \[\begin{equation}\label{eqn:7:vr_si} V_R = \frac{2\,(\sqrt{K}-1)^2}{n\,R\,\beta_3} \end{equation}\] and the reference current is then \[\begin{equation} I_b = \frac{V_R}{R} = \frac{2\,(\sqrt{K}-1)^2}{n\,R^2\,\beta_3}. \end{equation}\] The reference voltage and current are now process and temperature dependent through the \(R\) and \(\beta_3\) terms.

7.8.3.3 Any mode of inversion

We can also analyze the circuit to get an expression of the reference voltage \(V_R\) valid for any mode of inversion of M₁ and M₃. Since they share the same gate, they have the same pinch-off voltage \(V_{P1}=V_{P3}=V_P\). Assuming that M₁ and M₃ are in saturation, we can then express the normalized voltages as \[\begin{align} v_p &= 2\,q_{s1} + \ln(q_{s1}),\\ v_p-v_r &= 2\,q_{s3} + \ln(q_{s3}), \end{align}\] We can solve them to express \(v_r \triangleq V_R/U_T\) as \[\begin{equation}\label{eqn:7:vr} v_r \triangleq \frac{V_R}{U_T} = 2\,(q_{s1}-q_{s3})+\ln\left(\frac{q_{s1}}{q_{s3}}\right). \end{equation}\] \(q_{s1}\) and \(q_{s3}\) can be expressed in terms of the inversion coefficients \(IC_1\) and \(IC_3\) according to \[\begin{align} q_{s1} &= \frac{\sqrt{4\,IC_1+1}-1}{2},\label{eqn:7:qs1}\\ q_{s3} &= \frac{\sqrt{4\,IC_3+1}-1}{2}.\label{eqn:7:qs3} \end{align}\] Since the currents in M₁ and M₃ are equal, we have \[\begin{equation} I_{spec1}\,IC_1 = I_{spec3}\,IC_3. \end{equation}\] Because \(I_{spec3} = K\,I_{spec1}\), the inversion coefficient of M₁ is \(K\)-times larger than that of M₃ \[\begin{equation} IC_1 = K\,IC_3. \end{equation}\] Replacing \(IC_3\) by \(IC_1/K\) in \(\eqref{eqn:7:qs3}\) results in \[\begin{equation}\label{eqn:7:qs3_ic1} q_{s3} = \frac{\sqrt{4\,IC_1/K+1}-1}{2}. \end{equation}\] We can then set the inversion coefficient of M₁ \(IC_1\), calculate \(q_{s1}\) and \(q_{s3}\) using \(\eqref{eqn:7:qs1}\) and \(\eqref{eqn:7:qs3_ic1}\) and finally \(v_r\) with \(\eqref{eqn:7:vr}\). The reference voltage normalized to \(U_T\) is plotted versus \(IC_1\) for different values of \(K\) in Figure 85.

Figure 85: Reference voltage versus inversion coefficient \(IC_1\) of M₁.

The asymptote in weak inversion is \[\begin{equation} v_r = \ln(K), \end{equation}\] whereas in strong inversion it becomes proportionnal to \(\sqrt{IC_1}\) according to \[\begin{equation}\label{eqn:7:vr_ic_si} v_r = 2\,\sqrt{IC_1}\,\left(1-\frac{1}{\sqrt{K}}\right). \end{equation}\]

How is \(\eqref{eqn:7:vr_ic_si}\) different than \(\eqref{eqn:7:vr_si}\)? In strong inversion, \(\sqrt{IC_1}=V_P/(2\,U_T)\). Replacing in \(\eqref{eqn:7:vr_ic_si}\), we get \[\begin{equation}\label{eqn:7:vr_ic_si2} V_R = V_P\,\left(1-\frac{1}{\sqrt{K}}\right). \end{equation}\] Now \(V_R\) imposes the bias current \(I_b\) through the resistance \(R\) according to \[\begin{equation}\label{eqn:7:ib_vp_vr} I_b = \frac{V_R}{R} = \frac{n\,\beta_3}{2}\,(V_P-V_R)^2. \end{equation}\] Solving \(\eqref{eqn:7:vr_ic_si2}\) and \(\eqref{eqn:7:ib_vp_vr}\) for \(V_R\) gives \(\eqref{eqn:7:vr_si}\).

7.8.3.4 Start-up

Looking at Figure 84 (b), we see that there is another intersection of the 45 degree line and the M₁-M₃ characteristics, namely point Q. Forcing \(I_{in}\) to be equal to \(I_{out}\) does not neceessarly garantee that the circuit will operate at the equilibrium point P [24]. Indeed, having zero current flowing in M₁ and M₂ and M₃ and M₄ is theoretically possible even for a non-zero supply voltage, if the gate voltages of M₁-M₃ remains at ground and the gate voltages of M₂-M₄ remain at \(V_{DD}\). However, the second equilibrium point Q at the origin is unstable, provided that the leakage current coming from M₃ is larger than that of M₁, which is usually the case since M₃ is made \(K\)-times larger than M₁ [22]. Therefore the only stable equilibrium point is point P [22] [23]. We will check this in more details below.

Having a closer look at the circuit of Figure 83 (a) we realize that it is actually a positive feedback loop. Indeed, if we open the loop by disconnecting the drain of M₂, we can calculate the small-signal loop gain \(L = \Delta I_{D2}/\Delta I_{D1}\). Since the pMOS current mirror gain is one, the loop gain is actually equal to the small-signal current gain \(A_i \triangleq \Delta I_{out}/\Delta I_{in}\) of the core circuit of Figure 84 (a). To derive the small-signal current gain \(A_i\), we first perform a large-signal analysis of the circuit shown in Figure 84 (a) assuming that M₁-M₃ are biased in weak inversion and in saturation. The normalized input and output currents are given by \[\begin{align} i_{in} &\triangleq \frac{I_{in}}{I_{spec1}} = e^{v_p},\\ i_{out} &\triangleq \frac{I_{out}}{I_{spec1}} =K \cdot e^{v_p-v_r}, \end{align}\] where \[\begin{equation} v_r \triangleq \frac{V_R}{U_T} = r \cdot i_{out}, \end{equation}\] with \(r \triangleq K \cdot R \cdot G_{spec1}\). Note that \(I_{in}\) and \(I_{out}\) are normalized by the same normalization factor \(I_{spec1}\) so that \(i_{out}/i_{in} = I_{out}/I_{in}\). Therefore, \(i_{in}\) corresponds to the inversion coefficient of M₁. However, \(i_{out}\) is not equal to the inversion coefficient of M₃ but is \(K\)-times larger \(i_{out}=K \cdot IC_3\).

We cannot solve the above equations for expressing \(i_{out}\) in terms of \(i_{in}\), because it is a transcendental equation. However, we can express the input current \(i_{in}\) in terms of the output current \(i_{out}\) according to \[\begin{equation}\label{eqn:7:iin_iout} i_{in} = \frac{i_{out}}{K} \cdot e^{r \cdot i_{out}}. \end{equation}\]

Figure 86: Output current versus input current for M₁-M₃in weak inversion.

Equation \(\eqref{eqn:7:iin_iout}\) is plotted in Figure 86 for \(K=10\) and for a normalized resistance value \(r\) such that the \(i_{out}\) versus \(i_{in}\) characteristic crosses the 45\(^{\circ}\) line at \(i_{cross} = 0.08\). At this point \(i_{out} =i_{in}\) and \(v_r = \ln(K)\) and therefore \(r = \ln(K)/i_{cross}\) resulting in \(r =28.8\).

As shown by the red curve in Figure 86, when the input current increases starting from zero (point Q), the voltage \(v_r\) is still zero and the current gain is equal to \(K\) which is larger than one. This means that point Q of the closed-loop circuit of Figure 83 (a) is actually unstable because any leakage current at the input is amplified until the stable point P is reached. As the input current increases further, a voltage \(v_r\) develops across the resistance and the output current becomes smaller than \(K \cdot i_{in}\) until it reaches the 45\(^{\circ}\) line where \(i_{out}\) becomes equal to \(i_{in}\) (point P). This corresponds to the stable point P for the closed-loop circuit of Figure 83 (a).

The small-signal current gain \(A_i \triangleq \Delta i_{out}/\Delta i_{in}\), corresponding to the derivative of the \(i_{out}\) versus \(i_{in}\) characteristic, decreases as \(i_{in}\) increases. The inverse of the small-signal current gain \(1/A_i\) can be calculated by differentiating \(\eqref{eqn:7:iin_iout}\) resulting in \[\begin{equation}\label{eqn:7:ai_iout} A_i \triangleq \frac{\Delta i_{out}}{\Delta i_{in}} = \frac{\Delta I_{out}}{\Delta I_{in}} = K \cdot \frac{e^{-r \cdot i_{out}}}{1+r \cdot i_{out}} \end{equation}\] Equation \(\eqref{eqn:7:ai_iout}\) is plotted versus \(i_{in}\) in Figure 86 (right y-axis). The small-signal current gain \(A_i\) is starting at a value \(K\) larger than one and then decreases very sharply to reach a value much smaller than one when \(i_{in}\) reaches \(i_{out}\). This shows that point P of the closed-loop circuit of Figure 83 (a) is actually stable.

In many low-power applications, the circuits are turned-off and need to wake-up when needed. If the difference in leakage currents between M₃ and M₁ is small, it might take too long to reach the equilibrium point [23]. It is then necessary to add a start-up circuit to accelerate the power-up process. There are many possible startup circuits, but the main requirement is that the additional start-up circuit does not consume any current when the Vittoz reference circuit has reached its equilibrium point. One possible start-up circuit is shown in Figure 87 [25] [23].

Figure 87: The Vittoz reference with its start-up circuit [25] [23].

Let’s assume that the power is switched off and that all the node capacitances are discharged. When the supply voltage is switched on, the pMOS transistor M₆ is turned on and drives a current that charges the parasitic capacitance at the gates of M₁ and M₃ and injects some current into M₁. This current gets amplified in the loop and the current in the reference circuit starts to increase until the circuit reaches its equilibrium point P. The current in M₆ is maximum at power-up but then decreases as capacitance \(C_S\) gets charged up to \(V_{DD}\) by transistor M₈, subsequently turning off transistor M₆ [23].

7.8.4 The Oguey current reference

Figure 88: The Oguey current reference [26].

The resistance of the Vittoz reference of Figure 83 can advantageously be replaced by a transistor operating in the linear region. This is done in the Oguey current reference shown in Figure 88 [26], where a nMOS current mirror M₅-M₇ has been added to the Vittoz reference of Figure 83. Transistor M₅ is made \(A\)-times larger than M₇ (i.e. \(\beta_5 = A \cdot \beta_7\)).

If we assume that M₁-M₃ are biased in weak inversion, then \(V_R\) is given by \(\eqref{eqn:7:vr_wi}\). If we assume that M₅-M₇ are biased in strong inversion, it can be shown that the generated bias current is given by \[\begin{equation}\label{eqn:7:ib_oguey} I_b = I_{spec7}\,\left(\frac{A\,\ln(K)}{2}\right)^2\,\left(1+\sqrt{1-\frac{1}{A}}\right)^2. \end{equation}\] Since \(I_{spec5} = A\,I_{spec7}\), \(I_b\) is also proportional to \(I_{spec5}\) according to \[\begin{equation} I_b = I_{spec5}\,A\,\left(\frac{\ln(K)}{2}\right)^2\,\left(1+\sqrt{1-\frac{1}{A}}\right)^2. \end{equation}\] If we can make \(A \gg 1\), \(I_b\) simplifies to \[\begin{equation}\label{eqn:7:ib_oguey_app} I_b \cong I_{spec7}\,A^2\,\ln^2(K) = I_{spec5}\,A\,\ln^2(K). \end{equation}\]

Figure 89: Drain currents of M₅-M₇ versus their drain voltage.

Since M₅-M₇ share the same gate they have the same gate voltage and hence the same pinch-off voltage \(V_{P5} = V_{P7}\). If the drain of M₅ was not connected to M₃ and had a value larger than \(V_{P5}\), as shown in Figure 89, M₅ would drive a current \(A\)-times larger than M₇. In this case M₅ and M₇ would also have the same inversion coefficient \[\begin{equation} IC_5 = IC_7 = \frac{I_b}{I_{spec7}} = \frac{A\,I_b}{I_{spec5}} = (A\,\ln(K))^2. \end{equation}\] However, the drain voltage of M₅ is imposed by M₃ to \(V_R = U_T\,\ln(K)\) and the drain current is reduced to \(I_b\), pushing M₅ into the linear region as illustrated in Figure 89. M₇ being in saturation, its inversion coefficient remains unchanged and the inversion coefficient of M₅ is actually equal to its normalized forward current \(i_{f5}\) \[\begin{equation} IC_7 = i_{f5} = (A\,\ln(K))^2. \end{equation}\] The pinch-off voltage is then given by \[\begin{equation} V_{P7} = V_{P5} = 2\,U_T\,\sqrt{IC_7} = 2\,U_T\,A\,\ln(K). \end{equation}\]

The reference current \(I_b\) given by \(\eqref{eqn:7:ib_oguey}\) or \(\eqref{eqn:7:ib_oguey_app}\) is proportionnal to the specific current \(I_{spec5}\) or \(I_{spec7}\). This means that this current reference can be used to extract the specific current and therefore the specific current per square for nMOS transistors. Of course an additional p-type current reference is then needed to extract the specific current per square for pMOS transistors. We can therefore use the Oguey current reference to bias any nMOS transistor M_x at a given inversion coefficient \(IC_x\) by means of the bias current \(I_b\). Indeed, if we impose the bias current \(I_b\) to transistor M_x, then \(I_x=I_b\) and therefore \(IC_x \cdot I_{specx} = IC_7 \cdot I_{spec7}\) or \(IC_x \cdot W_x/L_x = IC_7 \cdot W_7/L_7\). In order to bias transistor M_x at an inversion coefficient \(IC_x\), its aspect ratio needs to be equal to \[\begin{equation} \frac{W_x}{L_x} = \frac{IC_7}{IC_x} \cdot \frac{W_7}{L_7}. \end{equation}\] This ratio-based biasing technique is very powerful because it is basically independent of the particular value of the threshold voltage, as long as all the transistors (except M₅) remain in saturation.

Note that in the above example we have chosen M₇ as reference transistor. This is a good choice if we want M_x to be biased in strong inversion. For biasing M_x in weak inversion, it would be better to use M₁ or M₃ as reference transistor.

The reference current \(I_b\) is slightly temperature-dependent through the specific current which is proportional to \(\mu\,U_T^2 \propto \mu\,T^2\). Since the mobility scales as \(T^{-\alpha}\) with \(\alpha\) comprised between 2.2 and 2.42 for undoped Si and decreases for doped Si [27], the specific current is proportionnal to \(T^{2-\alpha}\) which can be small for doped Si.

Note

Note that the Oguey current reference [26] was actually already published by P. Heim in [28], where he also proposes some improvements such as increasing the the PTAT \(V_R\) voltage using stacked PTAT voltage sources presented in Section 7.8.2 combined with an additional cascode transistor to reduce the effect of the output conductances of M₃ [28].

7.9 References

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[2]

F. Krummenacher, “Micropower Switched Capacitor Biquadratic Cell,” IEEE Journal of Solid-State Circuits, vol. 17, no. 3, pp. 507–512, 1982.

[3]

E. Sackinger and W. Guggenbuhl, “A high-swing, high-impedance MOS cascode circuit,” IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 289–298, 1990, doi: 10.1109/4.50316.

[4]

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[5]

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[6]

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[7]

E. Vittoz, “Micropower techniques,” in Design of VLSI circuits for telecommunication and signal processing, J. Franca and Y. Tsividis, Eds., Englewood Cliffs, NJ: Prentice-Hall, 1994, pp. 53–96.

[8]

C. C. Enz and E. A. Vittoz, “CMOS low-power analog circuit design,” in Emerging technologies, tutorial for 1996 int. Symp. On circuits and systems, R. Cavin and W. Liu, Eds., Piscataway, NJ: IEEE Service Center, 1996, pp. 79–133.

[9]

E. Vittoz, C. Enz, and F. Krummenacher, “A basic property of MOS transistors and its circuit implications,” in Proc. of the 2003 Workshop on Compact Modeling (WCM), https://ewh.ieee.org/r5/denver/sscs/References/2003_02_Vittoz.pdf, 2003.

[10]

C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design, 1^{st} ed. John Wiley, 2006.

[11]

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[12]

E. Vittoz, “Microwatt switched capacitor circuit design,” Electrocomponent Science and Technology, pp. 263–273, 1982, doi: 10.1155/APEC.9.263.

[13]

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[15]

R. G. Carvajal et al., “The flipped voltage follower: A useful cell for low-voltage low-power circuit design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1276–1291, 2005, doi: 10.1109/TCSI.2005.851387.

[16]

J. Ramirez-Angulo et al., “Comparison of conventional and new flipped voltage structures with increased input/output signal swing and current sourcing/sinking capabilities,” in 48th midwest symposium on circuits and systems, 2005., 2005, pp. 1151–1154 Vol. 2. doi: 10.1109/MWSCAS.2005.1594310.

[17]

A. Sheikholeslami, “Voltage follower, part II [circuit intuitions],” IEEE Solid-State Circuits Magazine, vol. 15, no. 1, pp. 17–19, 2023, doi: 10.1109/MSSC.2022.3218083.

[18]

J. N. Babanezhad and R. Gregorian, “A programmable gain/loss circuit,” IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 1082–1090, 1987, doi: 10.1109/JSSC.1987.1052858.

[19]

V. I. Prodanov and M. M. Green, “CMOS Current Mirrors With Reduced Input and Output Voltage Requirements,” Electronics Letters, vol. 32, no. 2, pp. 104–105, 1996.

[20]

P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge: Cambridge University Press, 2017.

[21]

E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operations,” Solid-State Circuits, IEEE Journal of, vol. 12, no. 3, pp. 224–231, 1977.

[22]

E. Vittoz, “Micropower Techniques,” in Design of analog-digital VLSI circuits for telecommunications and signal processing, J. Franca and Y. Tsividis, Eds., Prentice-Hall, 1994.

[23]

M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling. Cambridge University Press, 2010.

[24]

B. Murmann, Analysis and Design of Elementary MOS Amplifier Stages, 1-\(^{st}\) ed. National Technology; Science Press, 2013. Available: https://github.com/bmurmann/Book-on-MOS-stages/blob/main/book/Analysis%20and%20Design%20of%20Elementary%20MOS%20Amplifier%20Stages.pdf

[25]

G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutri, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 151–154, 2003, doi: 10.1109/JSSC.2002.806266.

[26]

H. J. Oguey and D. Aebischer, “CMOS current reference without resistance,” Solid-State Circuits, IEEE Journal of, vol. 32, no. 7, pp. 1132–1135, 1997.

[27]

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3^{rd} ed. John Wiley, 2006. Available: https://ia601608.us.archive.org/5/items/PhysicsOfSemiconductorDevices_855/PhysicsOfSemiconductorDevices3rdEdition-S.M.SzeAndKwokK.Ng.pdf

[28]

P. Heim, S. R. Schultz, and M. A. Jabri, “Technology-independent biasing technique for CMOS analogue micropower implementations of neural networks,” in Proc. Sixth australian conf. On neural networks, Sydney, Australia, 1995, pp. 9–12.